Dataflow modelling languages are highly effective for creating efficient implementations of signal processing operations on embedded and edge computing devices. However, they lack general constructs to compactly describe regular scalable structures, as required by modern large-scale signal processing and machine learning operations. This paper describes a framework to do that. It extends the Processing Graph Method coordination language with a switch construct which allows scalable, regular connectivity to be compactly expressed for compile-time analysis and elaboration. It shows how switches can merge, split and permute groups of connections and can express recognised topological structures - such as chains, rings, butterflys and multicast operations - despite its general nature. It is applied to the description of large-scale FFT and Artificial Neural Network (ANN) operators.
|Title of host publication||2020 IEEE Workshop on Signal Processing Systems (SiPS 2020): Proceedings|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||6|
|Publication status||Published - 23 Sep 2020|
|Event||34th IEEE Workshop on Signal Processing Systems, SiPS 2020 - Virtual, Coimbra, Portugal|
Duration: 20 Oct 2020 → 22 Oct 2020
|Name||IEEE Workshop on Signal Processing Systems (SiPS): Design and Implementation: Proceedings|
|Conference||34th IEEE Workshop on Signal Processing Systems, SiPS 2020|
|Period||20/10/2020 → 22/10/2020|
Bibliographical notePublisher Copyright:
© 2020 IEEE.
Copyright 2020 Elsevier B.V., All rights reserved.
- Graph Coordination
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Signal Processing
- Applied Mathematics
- Hardware and Architecture