Hardware level approximations

In the past two decades approximation techniques have been applied at the circuit and microarchitecture level for exploiting the error-resilient nature of many applications. The majority of such schemes aim to save energy by trading off computation quality and effort expended in logic and memory circuits. Common principle of such schemes is the approximation of certain parts of the logic and memory array using low-cost logic gates, bit-cells, or relaxed fault correction schemes. A wealth body of work also exists that targets to redesign application-specific and general-purpose processing cores for minimizing the cost of mitigating timing and memory errors induced by voltage down-scaling and/or process variations. The chapter categorizes such frameworks and overviews the basic principles behind the proposed schemes.