Abstract
A hardware performance analysis of the SHACAL-2 encryption algorithm is presented in this paper. SHACAL-2 was one of four symmetric key algorithms chosen in the New European Schemes for Signatures, Integrity and Encryption (NESSIE) initiative in 2003. The paper describes a fully pipelined encryption SHACAL-2 architecture implemented on a Xilinx Field Programmable Gate Array (FPGA) device that achieves a throughput of over 25 Gbps. This is the fastest private key encryption algorithm architecture currently available. The SHACAL-2 decryption algorithm is also defined in the paper as it was not provided in the NESSIE submission.
| Original language | English |
|---|---|
| Pages (from-to) | 478-484 |
| Number of pages | 7 |
| Journal | IEE Proceedings - Circuits, Devices and Systems |
| Volume | 152 (5) |
| Issue number | 5 |
| DOIs | |
| Publication status | Published - Oct 2005 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering