SoC systems are now being increasingly constructed using a hierarchy of subsystems or silicon Intellectual Property (IP) cores. The key challenge is to use these cores in a highly efficient manner which can be difficult as the internal core structure may not be known. A design methodology based on synthesizing hierarchical circuit descriptions is presented. The paper employs the MARS synthesis scheduling algorithm within the existing IRIS synthesis flow and details how it can be enhanced to allow for design exploration of IP cores. It is shown that by accessing parameterised expressions for the datapath latencies in the cores, highly efficient FPGA solutions can be achieved. Hardware sharing at both the hierarchical and flattened levels is explored for a normalized lattice filter and results are presented.
|Number of pages||5|
|Journal||Conference Record of the Asilomar Conference on Signals, Systems and Computers|
|Publication status||Published - Nov 2003|
|Event||37th Asilomar Conference on Signals, Systems and Computers - Pacific Grove, United States|
Duration: 01 Nov 2003 → 01 Nov 2003
Bibliographical noteCopyright 2008 Elsevier B.V., All rights reserved.
ASJC Scopus subject areas
- Hardware and Architecture
- Signal Processing
- Electrical and Electronic Engineering