Abstract
A high-sample rate 3D median filtering processor architecture is proposed, based on a novel 3D median filtering algorithm, that can reduce the computing complexity in comparison with the traditional bubble sorting algorithm. A 3 x 3 x 3 filter processor is implemented in VHDL, and the simulation verifies that the processor can process a 128 x 128 x 96 MRI image in 0.03 seconds while running at 50 MHz.
Original language | English |
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Pages (from-to) | 1379-1381 |
Number of pages | 3 |
Journal | Electronics Letters |
Volume | 42 |
Issue number | 24 |
DOIs | |
Publication status | Published - 2006 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering