High performance DSP ASIC for multiply, divide and square root

R. F. Woods, S. E. McQuillan, J. V. McCanny

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The design of a high-speed ASIC that combines the operations of multiplication, division and square root is described. The chip is based on a systolic array architecture that uses a redundant number system and allows multiplication, division, and square root to be combined on the same hardware. The chip has been designed using a 1.5- mu m, double-metal CMOS technology, operates on 16-b sign magnitude data, and has a throughput rate of 40 Msample/s for each operation.

Original languageEnglish
Title of host publicationProceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992
PublisherIEEE Computer Society
Pages209-213
Number of pages5
ISBN (Electronic)0780307682
DOIs
Publication statusPublished - 21 Sep 1992
Event5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 - Rochester, United States
Duration: 21 Sep 199225 Sep 1992

Conference

Conference5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992
CountryUnited States
CityRochester
Period21/09/199225/09/1992

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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