Abstract
The design of a high-speed ASIC that combines the operations of multiplication, division and square root is described. The chip is based on a systolic array architecture that uses a redundant number system and allows multiplication, division, and square root to be combined on the same hardware. The chip has been designed using a 1.5- mu m, double-metal CMOS technology, operates on 16-b sign magnitude data, and has a throughput rate of 40 Msample/s for each operation.
Original language | English |
---|---|
Title of host publication | Proceedings - 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 209-213 |
Number of pages | 5 |
ISBN (Electronic) | 0780307682 |
DOIs | |
Publication status | Published - 21 Sept 1992 |
Event | 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 - Rochester, United States Duration: 21 Sept 1992 → 25 Sept 1992 |
Conference
Conference | 5th Annual IEEE International ASIC Conference and Exhibit, ASIC 1992 |
---|---|
Country/Territory | United States |
City | Rochester |
Period | 21/09/1992 → 25/09/1992 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering