High performance IIR filter chip and its evaluation system

R. L. Walke*, R. A. Evans, R. F. Woods, G. Floyd, K. W. Wood

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A highly flexible programmable IIR filter chip has been designed and fabricated to commercial requirements within a collaborative project involving several industrial partners. The device, which is being demonstrated at the conference, uses 8 highly regular 16bit array multiplier-accumulators which have been pipelined to achieve an overall computational rate of 30MHz using a 1 micron gate array process. Most significant bit first arithmetic has been employed to achieve the target 15MHz sample rate whilst implementing an 8th order filter. The paper reviews the principles behind the filter chip and its architecture, and describes a modular system which has been built to facilitate its demonstration and evaluation.

Original languageEnglish
Title of host publicationProceedings of the International Conference on Application Specific Array Processors
Publisher IEEE
Pages22-30
Number of pages9
Publication statusPublished - 01 Dec 1994
Externally publishedYes
EventProceedings of the 1994 International Conference on Application Specific Array Processors - San Francisco, United States
Duration: 22 Aug 199424 Aug 1994

Publication series

NameProceedings of the International Conference on Application Specific Array Processors
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISSN (Print)1063-6862

Conference

ConferenceProceedings of the 1994 International Conference on Application Specific Array Processors
CountryUnited States
CitySan Francisco
Period22/08/199424/08/1994

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications

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