@inproceedings{355963006cfc4009919c2c88ce10cb40,
title = "High performance IIR filter chip and its evaluation system",
abstract = "A highly flexible programmable IIR filter chip has been designed and fabricated to commercial requirements within a collaborative project involving several industrial partners. The device, which is being demonstrated at the conference, uses 8 highly regular 16bit array multiplier-accumulators which have been pipelined to achieve an overall computational rate of 30MHz using a 1 micron gate array process. Most significant bit first arithmetic has been employed to achieve the target 15MHz sample rate whilst implementing an 8th order filter. The paper reviews the principles behind the filter chip and its architecture, and describes a modular system which has been built to facilitate its demonstration and evaluation.",
author = "Walke, {R. L.} and Evans, {R. A.} and Woods, {R. F.} and G. Floyd and Wood, {K. W.}",
year = "1994",
month = dec,
day = "1",
doi = "10.1109/ASAP.1994.331819",
language = "English",
isbn = "0818665173",
series = "Proceedings of the International Conference on Application Specific Array Processors",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "22--30",
booktitle = "Proceedings of the International Conference on Application Specific Array Processors",
address = "United States",
note = "Proceedings of the 1994 International Conference on Application Specific Array Processors ; Conference date: 22-08-1994 Through 24-08-1994",
}