High performance single-chip fpga rijndael algorithm implementations

Research output: Chapter in Book/Report/Conference proceedingConference contribution

75 Citations (Scopus)

Abstract

This paper describes high performance single-chip FPGA implementations of the new Advanced Encryption Standard (AES) algorithm, Rijndael. The designs are implemented on the Virtex-E FPGA family of devices. FPGAs have proven to be very effective in implementing encryption algorithms. They provide more flexibility than ASIC implementations and produce higher data-rates than equivalent software implementations. A novel, generic, parameterisable Rijndael encryptor core capable of supporting varying key sizes is presented. The 192-bit key and 256-bit key designs run at data rates of 5.8 Gbits/sec and 5.1 Gbits/sec respectively. The 128-bit key encryptor core has a throughput of 7 Gbits/sec which is 3.5 times faster than similar existing hardware designs and 21 times faster than known software implementations, making it the fastest single-chip FPGA Rijndael encryptor core reported to date. A fully pipelined single-chip 128-bit key Rijndael encryptor/decryptor core is also presented. This design runs at a data rate of 3.2 Gbits/sec on a Xilinx Virtex-E XCV3200E-8-CG1156 FPGA device. There are no known singlechip FPGA implementations of an encryptor/decryptor Rijndael design.

Original languageEnglish
Title of host publicationCryptographic Hardware and Embedded Systems - CHES 2001 - 3rd International Workshop, Proceedings
PublisherSpringer-Verlag
Pages65-76
Number of pages12
ISBN (Print)3540425217
Publication statusPublished - 01 Jan 2001
Event3rd International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2001 - Paris, France
Duration: 14 May 200116 May 2001

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume2162
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference3rd International Workshop on Cryptographic Hardware and Embedded Systems, CHES 2001
CountryFrance
CityParis
Period14/05/200116/05/2001

Keywords

  • AES
  • Encryption
  • FPGA implementation
  • Rijndael

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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