High performance VLSI architecture for division and square root

S.E. McQuillan, J.V. McCanny, R.F. Woods

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

A novel high performance bit parallel architecture to perform square root and division is proposed. Relevant VLSI design issues have been addressed. By employing redundant arithmetic and a semisystolic schedule, the throughput has been made independent of the size of the array.
Original languageEnglish
Pages (from-to)20-21
Number of pages2
JournalElectronics Letters
Volume27
Issue number1
Publication statusPublished - 01 Jan 1991

Bibliographical note

Copyright 2004 Elsevier B.V., All rights reserved.

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