High performance VLSI architecture for division and square root

S.E. McQuillan; J.V. McCanny; R.F. Woods

High performance VLSI architecture for division and square root

S.E. McQuillan
, J.V. McCanny
, R.F. Woods

Research output: Contribution to journal › Article › peer-review

Abstract

A novel high performance bit parallel architecture to perform square root and division is proposed. Relevant VLSI design issues have been addressed. By employing redundant arithmetic and a semisystolic schedule, the throughput has been made independent of the size of the array.

Original language	English
Pages (from-to)	20-21
Number of pages	2
Journal	Electronics Letters
Volume	27
Issue number	1
Publication status	Published - 01 Jan 1991

Bibliographical note

Cite this

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title = "High performance VLSI architecture for division and square root",

abstract = "A novel high performance bit parallel architecture to perform square root and division is proposed. Relevant VLSI design issues have been addressed. By employing redundant arithmetic and a semisystolic schedule, the throughput has been made independent of the size of the array.",

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High performance VLSI architecture for division and square root

Abstract

Bibliographical note

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