High-radix systolic modular multiplication on reconfigurable hardware

C McIvor*, M McLoone, JV McCanny

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

22 Citations (Scopus)


The overall aim of the work presented in this paper has been to develop Montgomery modular multiplication architectures suitable for implementation on modern reconfigurable hardware. Accordingly, novel high-radix systolic array Montgomery multiplier designs are presented, as we believe that the inherent regular structure and absence of global interconnect associated with these, make them well-suited for implementation on modern FPGAs. Unlike previous approaches, each processing element (PE) comprises both an adder and a multiplier. The inclusion of a multiplier in the PE means that the need to pre-compute or store any multiples of the operands is avoided. This also allows very high-radix implementations to be realised, further reducing the amount of clock cycles per modular multiplication, while still maintaining a competitive critical delay. For demonstrative purposes, 512-bit and 1024-bit FPGA implementations using radices of 2(8) and 2(16) are presented. The subsequent throughput rates are the fastest reported to date.

Original languageEnglish
Title of host publicationFPT 05: 2005 IEEE International Conference on Field Programmable Technology, Proceedings
EditorsG Brebner, S Chakraborty, WF Wong
Place of PublicationNEW YORK
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages6
ISBN (Print)0-7803-9407-0
Publication statusPublished - 2005
Event4th IEEE International Conference on Field Programmable Technology - Singapore, Singapore
Duration: 11 Dec 200514 Dec 2005


Conference4th IEEE International Conference on Field Programmable Technology



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