High sampling rate retimed DLMS filter implementations in Virtex-II FPGA

Y. Yi, Roger Woods, L.K. Ting, Colin Cowan

Research output: Contribution to conferencePaper

12 Citations (Scopus)
Original languageEnglish
Pages139-145
Number of pages7
Publication statusPublished - Oct 2002
EventIEEE Workshop on Signal Processing Systems (SIPS 02) - San Diego, California, United States
Duration: 01 Oct 200201 Oct 2002

Conference

ConferenceIEEE Workshop on Signal Processing Systems (SIPS 02)
CountryUnited States
CitySan Diego, California
Period01/10/200201/10/2002

Cite this

Yi, Y., Woods, R., Ting, L. K., & Cowan, C. (2002). High sampling rate retimed DLMS filter implementations in Virtex-II FPGA. 139-145. Paper presented at IEEE Workshop on Signal Processing Systems (SIPS 02), San Diego, California, United States.