High sampling rate retimed DLMS filter implementations in Virtex-II FPGA

Research output: Contribution to conference › Paper

Original language	English
Pages	139-145
Number of pages	7
Publication status	Published - Oct 2002
Event	IEEE Workshop on Signal Processing Systems (SIPS 02) - San Diego, California, United States Duration: 01 Oct 2002 → 01 Oct 2002

Conference	IEEE Workshop on Signal Processing Systems (SIPS 02)
Country	United States
City	San Diego, California
Period	01/10/2002 → 01/10/2002

Cite this

Yi, Y., Woods, R., Ting, L. K., & Cowan, C. (2002). High sampling rate retimed DLMS filter implementations in Virtex-II FPGA. 139-145. Paper presented at IEEE Workshop on Signal Processing Systems (SIPS 02), San Diego, California, United States.

@conference{5e67d304d289441da6cd030c18f0fae8,

title = "High sampling rate retimed DLMS filter implementations in Virtex-II FPGA",

author = "Y. Yi and Roger Woods and L.K. Ting and Colin Cowan",

year = "2002",

month = oct,

language = "English",

pages = "139--145",

note = "IEEE Workshop on Signal Processing Systems (SIPS 02) ; Conference date: 01-10-2002 Through 01-10-2002",

}