HIGH SPEED CMOS/SOS IMPLEMENTATION OF A BIT LEVEL SYSTOLIC CORRELATOR.

J.C. White, J.V. McCanny, A. McCabe, J. McWhirter, R. Evans

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

The fabrication and performance of the first bit-level systolic correlator array is described. The application of systolic array concepts at the bit level provides a simple and extremely powerful method for implementing high-performance digital processing functions. The resulting structure is highly regular, facilitating yield enhancement through fault-tolerant redundancy techniques and therefore ideally suited to implementation as a VLSI chip. The CMOS/SOS chip operates at 35 MHz, is fully cascadable and exhibits 64-stage correlation for 1-bit reference and 4-bit data. 7 refs.
Original languageEnglish
Pages (from-to)1161-1164
Number of pages4
JournalICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Publication statusPublished - 01 Jan 1986

Bibliographical note

Copyright 2004 Elsevier B.V., All rights reserved.

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