The fabrication and performance of the first bit-level systolic correlator array is described. The application of systolic array concepts at the bit level provides a simple and extremely powerful method for implementing high-performance digital processing functions. The resulting structure is highly regular, facilitating yield enhancement through fault-tolerant redundancy techniques and therefore ideally suited to implementation as a VLSI chip. The CMOS/SOS chip operates at 35 MHz, is fully cascadable and exhibits 64-stage correlation for 1-bit reference and 4-bit data. 7 refs.
|Number of pages||4|
|Journal||ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings|
|Publication status||Published - 01 Jan 1986|
Bibliographical noteCopyright 2004 Elsevier B.V., All rights reserved.
White, J. C., McCanny, J. V., McCabe, A., McWhirter, J., & Evans, R. (1986). HIGH SPEED CMOS/SOS IMPLEMENTATION OF A BIT LEVEL SYSTOLIC CORRELATOR. ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings, 1161-1164.