Abstract
In this brief, we realize different architectural techniques for improving the performance of post-quantum cryptography (PQC) algorithms when implemented as hardware accelerators on an application-specific integrated circuit (ASIC) platform. Having SABER as a case study, we designed a 256-bit wide architecture geared for high-speed cryptographic applications that incorporates smaller and distributed SRAM memory blocks. Moreover, we have adapted the building blocks of SABER to process 256-bit words. We have also used a buffering technique for efficient polynomial coefficient multiplications to reduce the clock cycle count. Finally, double-sponge functions are combined serially (one after another) in a high-speed KECCAK core to improve the hash operations of SHA/SHAKE. For key-generation, encapsulation, and decapsulation operations of SABER, our 256-bit wide accelerator with a single sponge function is 1.71x, 1.45x, and 1.78x faster than the raw clock cycle count of a serialized SABER design. Similarly, our 256-bit implementation with double-sponge functions takes 1.08x, 1.07x & 1.06x fewer clock cycles compared to its single-sponge counterpart. The studied optimization techniques are not specific to SABER - they can be utilized for improving the performance of other lattice-based PQC accelerators.
Original language | English |
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Pages (from-to) | 847-851 |
Number of pages | 5 |
Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
Volume | 71 |
Issue number | 2 |
Early online date | 08 May 2023 |
DOIs | |
Publication status | Published - 01 Feb 2024 |
Externally published | Yes |
Bibliographical note
Publisher Copyright:© 2004-2012 IEEE.
Keywords
- ASIC design
- cryptocore
- hardware accelerator
- PQC
- SABER
ASJC Scopus subject areas
- Electrical and Electronic Engineering