High Speed FPGA-based implementations of Delayed-LMS filters

Lok Kee Ting, Roger Woods, Colin Cowan

Research output: Contribution to journalArticle

44 Citations (Scopus)

Abstract

A variation of the least means squares (LMS) algorithm, called the delayed LMS (DLMS) algorithm is an ideally suited to achieve highly pipelined, adaptive digital filter implementations. The paper presents an efficient method of determining the delays in the DLMS filter and then transferring these delays using retiming in order to achieve fully pipelined circuit architectures for FPGA implementation. The method has been used to derive a series of retimed delayed LMS (RDLMS) architectures, which considerable reduce the number of delays and convergence time and give superior performance in terms of throughput rate when compared to previous work. Three circuit architectures and three hardware shared versions are presented which have been implemented using the Virtex-II FPGA technology resulting in a throughout rate of 182 Msample/s.
Original languageEnglish
Pages (from-to)113-131
Number of pages19
JournalJournal of VLSI Signal Processing
Volume39
Issue number1-2 SPEC.ISS.
Publication statusPublished - Jan 2005

ASJC Scopus subject areas

  • Information Systems
  • Signal Processing
  • Electrical and Electronic Engineering

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