Highly efficient, limited range multipliers for LUT-based FPGA architectures

Research output: Contribution to journal › Article › peer-review

Original language	English
Pages (from-to)	1113-1118
Number of pages	6
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	12(10)
Issue number	10
DOIs	https://doi.org/10.1109/TVLSI.2004.833399
Publication status	Published - Oct 2004

ASJC Scopus subject areas

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title = "Highly efficient, limited range multipliers for LUT-based FPGA architectures",

author = "Richard Turner and Roger Woods",

year = "2004",

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issn = "1063-8210",

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AU - Woods, Roger

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