HPMA-NTRU: high-performance polynomial multiplication accelerator for NTRU

Pengzhou He; Yazheng Tu; Ayesha Khalid; Maire O'Neill; Jiafeng Xie

doi:10.1109/DFT56152.2022.9962336

HPMA-NTRU: high-performance polynomial multiplication accelerator for NTRU

Pengzhou He, Yazheng Tu, Ayesha Khalid, Maire O'Neill, Jiafeng Xie

Queen's University Belfast

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

Along the rapid development of large-scale quantum computers, post-quantum cryptography (PQC) has drawn significant attention from research community recently as it is proven that the existing public-key cryptosystems are vulnerable to the quantum attacks. Meanwhile, the recent trend in the PQC field has gradually switched to the hardware acceleration aspect. Following this trend, this work presents a novel implementation of a High-performance Polynomial Multiplication hardware Accelerator for NTRU (HPMA-NTRU) under different parameter settings, one of the lattice-based PQC algorithm that is currently under the consideration by the National Institute of Standards and Technology (NIST) PQC standardization process. In total, we have carried out three layers of efforts to obtain the proposed work. First of all, we have proposed a new schoolbook algorithm based strategy to derive the desired polynomial multiplication algorithm for NTRU. Then, we have mapped the algorithm to build a high-performance polynomial multiplication hardware accelerator and have extended this hardware accelerator to different parameter settings with proper adjustment. Finally, through a series of complexity analysis and implementation based comparison, we have shown that the proposed hardware accelerator obtains better area-time complexities than the state-of-the-art one. The outcome of this work is important and will impact the ongoing NIST PQC standardization process and can be deployed further to construct efficient NTRU cryptoprocessors.

Original language	English
Title of host publication	35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022: Proceedings
Editors	Luca Cassano, Sreejit Chakravarty, Alberto Bosio
Publisher	Institute of Electrical and Electronics Engineers Inc.
Number of pages	6
ISBN (Electronic)	9781665459389
DOIs	https://doi.org/10.1109/DFT56152.2022.9962336
Publication status	Published - 30 Nov 2022
Event	35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022 - Austin, United States Duration: 19 Oct 2022 → 21 Oct 2022

Publication series

Name	Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT
Volume	2022-October
ISSN (Print)	2576-1501
ISSN (Electronic)	2765-933X

Conference

Conference	35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022
Country/Territory	United States
City	Austin
Period	19/10/2022 → 21/10/2022

Bibliographical note

Funding Information:
The first two authors, Pengzhou He and Yazheng Tu, contributed equally. The work of Jiafeng Xie was supported by NIST-60NANB20D203 and in part by NSF SaTC-2020625. Ayesha Khalid, Máire O’Neill were funded by EPSRC Quantum Communications Hub (EP/T001011/1).

Publisher Copyright:
© 2022 IEEE.

Keywords

High-performance
NTRU
polynomial multiplication hardware accelerator
post-quantum cryptography (PQC)

ASJC Scopus subject areas

Hardware and Architecture
Signal Processing
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/DFT56152.2022.9962336Licence: Unspecified

Cite this

He, P., Tu, Y., Khalid, A., O'Neill, M., & Xie, J. (2022). HPMA-NTRU: high-performance polynomial multiplication accelerator for NTRU. In L. Cassano, S. Chakravarty, & A. Bosio (Eds.), 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022: Proceedings (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 2022-October). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFT56152.2022.9962336

He, Pengzhou ; Tu, Yazheng ; Khalid, Ayesha et al. / HPMA-NTRU: high-performance polynomial multiplication accelerator for NTRU. 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022: Proceedings. editor / Luca Cassano ; Sreejit Chakravarty ; Alberto Bosio. Institute of Electrical and Electronics Engineers Inc., 2022. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT).

@inproceedings{94c65675849a4604af34391f40f9442a,

title = "HPMA-NTRU: high-performance polynomial multiplication accelerator for NTRU",

abstract = "Along the rapid development of large-scale quantum computers, post-quantum cryptography (PQC) has drawn significant attention from research community recently as it is proven that the existing public-key cryptosystems are vulnerable to the quantum attacks. Meanwhile, the recent trend in the PQC field has gradually switched to the hardware acceleration aspect. Following this trend, this work presents a novel implementation of a High-performance Polynomial Multiplication hardware Accelerator for NTRU (HPMA-NTRU) under different parameter settings, one of the lattice-based PQC algorithm that is currently under the consideration by the National Institute of Standards and Technology (NIST) PQC standardization process. In total, we have carried out three layers of efforts to obtain the proposed work. First of all, we have proposed a new schoolbook algorithm based strategy to derive the desired polynomial multiplication algorithm for NTRU. Then, we have mapped the algorithm to build a high-performance polynomial multiplication hardware accelerator and have extended this hardware accelerator to different parameter settings with proper adjustment. Finally, through a series of complexity analysis and implementation based comparison, we have shown that the proposed hardware accelerator obtains better area-time complexities than the state-of-the-art one. The outcome of this work is important and will impact the ongoing NIST PQC standardization process and can be deployed further to construct efficient NTRU cryptoprocessors. ",

keywords = "High-performance, NTRU, polynomial multiplication hardware accelerator, post-quantum cryptography (PQC)",

author = "Pengzhou He and Yazheng Tu and Ayesha Khalid and Maire O'Neill and Jiafeng Xie",

note = "Funding Information: The first two authors, Pengzhou He and Yazheng Tu, contributed equally. The work of Jiafeng Xie was supported by NIST-60NANB20D203 and in part by NSF SaTC-2020625. Ayesha Khalid, M{\'a}ire O{\textquoteright}Neill were funded by EPSRC Quantum Communications Hub (EP/T001011/1). Publisher Copyright: {\textcopyright} 2022 IEEE.; 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022 ; Conference date: 19-10-2022 Through 21-10-2022",

year = "2022",

month = nov,

day = "30",

doi = "10.1109/DFT56152.2022.9962336",

language = "English",

series = "Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

editor = "Luca Cassano and Sreejit Chakravarty and Alberto Bosio",

booktitle = "35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022: Proceedings",

address = "United States",

}

He, P, Tu, Y, Khalid, A , O'Neill, M & Xie, J 2022, HPMA-NTRU: high-performance polynomial multiplication accelerator for NTRU. in L Cassano, S Chakravarty & A Bosio (eds), 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022: Proceedings. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT, vol. 2022-October, Institute of Electrical and Electronics Engineers Inc., 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022, Austin, United States, 19/10/2022. https://doi.org/10.1109/DFT56152.2022.9962336

HPMA-NTRU: high-performance polynomial multiplication accelerator for NTRU. / He, Pengzhou; Tu, Yazheng; Khalid, Ayesha et al.
35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022: Proceedings. ed. / Luca Cassano; Sreejit Chakravarty; Alberto Bosio. Institute of Electrical and Electronics Engineers Inc., 2022. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 2022-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - HPMA-NTRU: high-performance polynomial multiplication accelerator for NTRU

AU - He, Pengzhou

AU - Tu, Yazheng

AU - Khalid, Ayesha

AU - O'Neill, Maire

AU - Xie, Jiafeng

N1 - Funding Information: The first two authors, Pengzhou He and Yazheng Tu, contributed equally. The work of Jiafeng Xie was supported by NIST-60NANB20D203 and in part by NSF SaTC-2020625. Ayesha Khalid, Máire O’Neill were funded by EPSRC Quantum Communications Hub (EP/T001011/1). Publisher Copyright: © 2022 IEEE.

PY - 2022/11/30

Y1 - 2022/11/30

N2 - Along the rapid development of large-scale quantum computers, post-quantum cryptography (PQC) has drawn significant attention from research community recently as it is proven that the existing public-key cryptosystems are vulnerable to the quantum attacks. Meanwhile, the recent trend in the PQC field has gradually switched to the hardware acceleration aspect. Following this trend, this work presents a novel implementation of a High-performance Polynomial Multiplication hardware Accelerator for NTRU (HPMA-NTRU) under different parameter settings, one of the lattice-based PQC algorithm that is currently under the consideration by the National Institute of Standards and Technology (NIST) PQC standardization process. In total, we have carried out three layers of efforts to obtain the proposed work. First of all, we have proposed a new schoolbook algorithm based strategy to derive the desired polynomial multiplication algorithm for NTRU. Then, we have mapped the algorithm to build a high-performance polynomial multiplication hardware accelerator and have extended this hardware accelerator to different parameter settings with proper adjustment. Finally, through a series of complexity analysis and implementation based comparison, we have shown that the proposed hardware accelerator obtains better area-time complexities than the state-of-the-art one. The outcome of this work is important and will impact the ongoing NIST PQC standardization process and can be deployed further to construct efficient NTRU cryptoprocessors.

AB - Along the rapid development of large-scale quantum computers, post-quantum cryptography (PQC) has drawn significant attention from research community recently as it is proven that the existing public-key cryptosystems are vulnerable to the quantum attacks. Meanwhile, the recent trend in the PQC field has gradually switched to the hardware acceleration aspect. Following this trend, this work presents a novel implementation of a High-performance Polynomial Multiplication hardware Accelerator for NTRU (HPMA-NTRU) under different parameter settings, one of the lattice-based PQC algorithm that is currently under the consideration by the National Institute of Standards and Technology (NIST) PQC standardization process. In total, we have carried out three layers of efforts to obtain the proposed work. First of all, we have proposed a new schoolbook algorithm based strategy to derive the desired polynomial multiplication algorithm for NTRU. Then, we have mapped the algorithm to build a high-performance polynomial multiplication hardware accelerator and have extended this hardware accelerator to different parameter settings with proper adjustment. Finally, through a series of complexity analysis and implementation based comparison, we have shown that the proposed hardware accelerator obtains better area-time complexities than the state-of-the-art one. The outcome of this work is important and will impact the ongoing NIST PQC standardization process and can be deployed further to construct efficient NTRU cryptoprocessors.

KW - High-performance

KW - NTRU

KW - polynomial multiplication hardware accelerator

KW - post-quantum cryptography (PQC)

U2 - 10.1109/DFT56152.2022.9962336

DO - 10.1109/DFT56152.2022.9962336

M3 - Conference contribution

AN - SCOPUS:85143773834

T3 - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT

BT - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022: Proceedings

A2 - Cassano, Luca

A2 - Chakravarty, Sreejit

A2 - Bosio, Alberto

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022

Y2 - 19 October 2022 through 21 October 2022

ER -

He P, Tu Y, Khalid A , O'Neill M, Xie J. HPMA-NTRU: high-performance polynomial multiplication accelerator for NTRU. In Cassano L, Chakravarty S, Bosio A, editors, 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022: Proceedings. Institute of Electrical and Electronics Engineers Inc. 2022. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT). doi: 10.1109/DFT56152.2022.9962336

HPMA-NTRU: high-performance polynomial multiplication accelerator for NTRU

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

Fingerprint

Cite this