Adders and multipliers are key operations in DSP systems. The power consumption of adders is well understood but there are few detailed results on the choice of multipliers available. This paper considers how the power consumption of a number of multiplier structures such as Carry-Save array and Wallace Tree multipliers varies with data wordlengths and different layout strategies. In all cases, results were obtained from EPIC PowerMill simulations of actual synthesised circuit layouts. Analysis of the results highlights the effects of routing and interconnect optimization for low power operation and gives clear indications on choice of multiplier structure and design flow for the rapid design of DSP systems.
|Number of pages||3|
|Publication status||Published - 01 Jan 1998|
|Event||Proceedings of the 1998 International Symposium on Low Power Electronics and Design - Monterey, United States|
Duration: 10 Aug 1998 → 12 Aug 1998
|Conference||Proceedings of the 1998 International Symposium on Low Power Electronics and Design|
|Period||10/08/1998 → 12/08/1998|
ASJC Scopus subject areas