Impact of data characteristics and hardware topology on hardware selection for low power DSP

Gareth Keane; Jonathan Spanier; Roger Woods

Impact of data characteristics and hardware topology on hardware selection for low power DSP

Gareth Keane^*, Jonathan Spanier, Roger Woods

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

4 Citations (Scopus)

Abstract

Adders and multipliers are key operations in DSP systems. The power consumption of adders is well understood but there are few detailed results on the choice of multipliers available. This paper considers how the power consumption of a number of multiplier structures such as Carry-Save array and Wallace Tree multipliers varies with data wordlengths and different layout strategies. In all cases, results were obtained from EPIC PowerMill simulations of actual synthesised circuit layouts. Analysis of the results highlights the effects of routing and interconnect optimization for low power operation and gives clear indications on choice of multiplier structure and design flow for the rapid design of DSP systems.

Original language	English
Pages	94-96
Number of pages	3
Publication status	Published - 01 Jan 1998
Externally published	Yes
Event	Proceedings of the 1998 International Symposium on Low Power Electronics and Design - Monterey, United States Duration: 10 Aug 1998 → 12 Aug 1998

Conference

Conference	Proceedings of the 1998 International Symposium on Low Power Electronics and Design
Country/Territory	United States
City	Monterey
Period	10/08/1998 → 12/08/1998

ASJC Scopus subject areas

Engineering(all)

Cite this

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title = "Impact of data characteristics and hardware topology on hardware selection for low power DSP",

abstract = "Adders and multipliers are key operations in DSP systems. The power consumption of adders is well understood but there are few detailed results on the choice of multipliers available. This paper considers how the power consumption of a number of multiplier structures such as Carry-Save array and Wallace Tree multipliers varies with data wordlengths and different layout strategies. In all cases, results were obtained from EPIC PowerMill simulations of actual synthesised circuit layouts. Analysis of the results highlights the effects of routing and interconnect optimization for low power operation and gives clear indications on choice of multiplier structure and design flow for the rapid design of DSP systems.",

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AU - Spanier, Jonathan

AU - Woods, Roger

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N2 - Adders and multipliers are key operations in DSP systems. The power consumption of adders is well understood but there are few detailed results on the choice of multipliers available. This paper considers how the power consumption of a number of multiplier structures such as Carry-Save array and Wallace Tree multipliers varies with data wordlengths and different layout strategies. In all cases, results were obtained from EPIC PowerMill simulations of actual synthesised circuit layouts. Analysis of the results highlights the effects of routing and interconnect optimization for low power operation and gives clear indications on choice of multiplier structure and design flow for the rapid design of DSP systems.

AB - Adders and multipliers are key operations in DSP systems. The power consumption of adders is well understood but there are few detailed results on the choice of multipliers available. This paper considers how the power consumption of a number of multiplier structures such as Carry-Save array and Wallace Tree multipliers varies with data wordlengths and different layout strategies. In all cases, results were obtained from EPIC PowerMill simulations of actual synthesised circuit layouts. Analysis of the results highlights the effects of routing and interconnect optimization for low power operation and gives clear indications on choice of multiplier structure and design flow for the rapid design of DSP systems.

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M3 - Paper

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T2 - Proceedings of the 1998 International Symposium on Low Power Electronics and Design

Y2 - 10 August 1998 through 12 August 1998

ER -

Impact of data characteristics and hardware topology on hardware selection for low power DSP

Abstract

Conference

ASJC Scopus subject areas

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