Impact of data characteristics and hardware topology on hardware selection for low power DSP

Gareth Keane*, Jonathan Spanier, Roger Woods

*Corresponding author for this work

Research output: Contribution to conferencePaper

4 Citations (Scopus)

Abstract

Adders and multipliers are key operations in DSP systems. The power consumption of adders is well understood but there are few detailed results on the choice of multipliers available. This paper considers how the power consumption of a number of multiplier structures such as Carry-Save array and Wallace Tree multipliers varies with data wordlengths and different layout strategies. In all cases, results were obtained from EPIC PowerMill simulations of actual synthesised circuit layouts. Analysis of the results highlights the effects of routing and interconnect optimization for low power operation and gives clear indications on choice of multiplier structure and design flow for the rapid design of DSP systems.

Original languageEnglish
Pages94-96
Number of pages3
Publication statusPublished - 01 Jan 1998
Externally publishedYes
EventProceedings of the 1998 International Symposium on Low Power Electronics and Design - Monterey, United States
Duration: 10 Aug 199812 Aug 1998

Conference

ConferenceProceedings of the 1998 International Symposium on Low Power Electronics and Design
CountryUnited States
CityMonterey
Period10/08/199812/08/1998

ASJC Scopus subject areas

  • Engineering(all)

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    Keane, G., Spanier, J., & Woods, R. (1998). Impact of data characteristics and hardware topology on hardware selection for low power DSP. 94-96. Paper presented at Proceedings of the 1998 International Symposium on Low Power Electronics and Design, Monterey, United States.