Implementation of a Heterogeneous-Reliability Memory Framework

Konstantinos Tovletoglou

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DRAM consumes up to 40% out of the total power dissipation in servers. Techniques try to reduce it by relaxing the DRAM timing parameters, such as refresh rate. However operation under relaxed parameters poses a threat to the reliability. To allow the operation of the system even when errors occur, recent schemes suggest the usage of heterogeneous-reliability memory. Critical data are protected in reliable memory, while the non-critical data are stored in unreliable memory with relaxed parameters that is more energy efficient.
Our aim is to develop a heterogeneous-reliability DRAM framework and implement it on a commodity server. The implementation of such a framework faces three major problems: i) the existence of hardware-based memory interleaving, implemented in all server memory controllers (MCUs), which does not allow to differentiate the address space of the two memory domains, reliable and unreliable, ii) if the interleaving is disabled, a solid performance overhead is introduced and finally iii) an easy to use interface does not exist for users to adopt this technology.
Original languageEnglish
Publication statusPublished - 06 Nov 2018
Event27th International Conference on Parallel Architectures and Compilation Techniques (PACT18) - Limassol, Cyprus
Duration: 01 Nov 201804 Nov 2018
Conference number: 27


Conference27th International Conference on Parallel Architectures and Compilation Techniques (PACT18)
Abbreviated titlePACT
Internet address


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