Abstract
This paper presents a novel FPGA implementation of a two dimensional (8×8) point Discrete Cosine Transform. It is shown how the development of a suitable architectural style can produce high quality circuit designs for a specific technology, in this case the Xilinx XC6200 series of FPGA. Distributed arithmetic and exploitation of parallelism and pipelining are used to produce a DCT implementation on a single FPGA that operates at 25 frames per second with VGA resolution which is the equivalent of 2 million multiplications or additions per second.
Original language | English |
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Pages | 541-550 |
Number of pages | 10 |
Publication status | Published - 01 Dec 1997 |
Externally published | Yes |
Event | Proceedings of the 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation - Leicester, United Kingdom Duration: 03 Nov 1997 → 05 Nov 1997 |
Conference
Conference | Proceedings of the 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation |
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Country/Territory | United Kingdom |
City | Leicester |
Period | 03/11/1997 → 05/11/1997 |
ASJC Scopus subject areas
- Signal Processing
- Media Technology