Implementation of the 2D DCT using a XILINX XC6264 FPGA

D. W. Trainor*, J. P. Heron, R. F. Woods

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

13 Citations (Scopus)

Abstract

This paper presents a novel FPGA implementation of a two dimensional (8×8) point Discrete Cosine Transform. It is shown how the development of a suitable architectural style can produce high quality circuit designs for a specific technology, in this case the Xilinx XC6200 series of FPGA. Distributed arithmetic and exploitation of parallelism and pipelining are used to produce a DCT implementation on a single FPGA that operates at 25 frames per second with VGA resolution which is the equivalent of 2 million multiplications or additions per second.

Original languageEnglish
Pages541-550
Number of pages10
Publication statusPublished - 01 Dec 1997
Externally publishedYes
EventProceedings of the 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation - Leicester, United Kingdom
Duration: 03 Nov 199705 Nov 1997

Conference

ConferenceProceedings of the 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation
Country/TerritoryUnited Kingdom
CityLeicester
Period03/11/199705/11/1997

ASJC Scopus subject areas

  • Signal Processing
  • Media Technology

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