Improved Reliability of FPGA-based PUF Identification Generator Design

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Abstract

Physical unclonable functions (PUFs), a new form of physical security primitive, enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs). Many PUF implementations have been proposed to generate these unique n-bit binary strings. However, they often offer insufficient uniqueness and reliability when implemented on FPGAs, and can consume excessive resources. To address these problems, in this paper we present an efficient, lightweight and scalable PUF identification (ID) generator circuit that offers a compact design with good uniqueness and reliability properties, and is specifically designed for FPGAs. A novel post-characterisation methodology is also proposed, which improves the reliability of a PUF without the need for any additional hardware resources. Moreover, the proposed postcharacterisation method can be generally used for any FPGA-based PUF designs. The PUF ID generator consumes 8.95% of the hardware resources of a low-cost Xilinx Spartan-6 LX9 FPGA and 0.81% of a Xilinx Artix-7 FPGA. Experimental results show good uniqueness, reliability, and uniformity with no occurrence of bit-aliasing. In particular, the reliability of the PUF is close to 100% over an environmental temperature range of 25 oC to 70 oC with ±10% variation in the supply voltage.
LanguageEnglish
Article number20
JournalACM Transactions on Reconfigurable Technology and Systems
Volume10
Issue number3
DOIs
Publication statusPublished - 03 Jul 2017

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Field programmable gate arrays (FPGA)
Hardware
Hardware security
Networks (circuits)
Electric potential
Costs
Temperature

Cite this

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title = "Improved Reliability of FPGA-based PUF Identification Generator Design",
abstract = "Physical unclonable functions (PUFs), a new form of physical security primitive, enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs). Many PUF implementations have been proposed to generate these unique n-bit binary strings. However, they often offer insufficient uniqueness and reliability when implemented on FPGAs, and can consume excessive resources. To address these problems, in this paper we present an efficient, lightweight and scalable PUF identification (ID) generator circuit that offers a compact design with good uniqueness and reliability properties, and is specifically designed for FPGAs. A novel post-characterisation methodology is also proposed, which improves the reliability of a PUF without the need for any additional hardware resources. Moreover, the proposed postcharacterisation method can be generally used for any FPGA-based PUF designs. The PUF ID generator consumes 8.95{\%} of the hardware resources of a low-cost Xilinx Spartan-6 LX9 FPGA and 0.81{\%} of a Xilinx Artix-7 FPGA. Experimental results show good uniqueness, reliability, and uniformity with no occurrence of bit-aliasing. In particular, the reliability of the PUF is close to 100{\%} over an environmental temperature range of 25 oC to 70 oC with ±10{\%} variation in the supply voltage.",
author = "Chongyan Gu and Neil Hanley and Maire O'Neill",
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AU - Gu, Chongyan

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AU - O'Neill, Maire

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N2 - Physical unclonable functions (PUFs), a new form of physical security primitive, enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs). Many PUF implementations have been proposed to generate these unique n-bit binary strings. However, they often offer insufficient uniqueness and reliability when implemented on FPGAs, and can consume excessive resources. To address these problems, in this paper we present an efficient, lightweight and scalable PUF identification (ID) generator circuit that offers a compact design with good uniqueness and reliability properties, and is specifically designed for FPGAs. A novel post-characterisation methodology is also proposed, which improves the reliability of a PUF without the need for any additional hardware resources. Moreover, the proposed postcharacterisation method can be generally used for any FPGA-based PUF designs. The PUF ID generator consumes 8.95% of the hardware resources of a low-cost Xilinx Spartan-6 LX9 FPGA and 0.81% of a Xilinx Artix-7 FPGA. Experimental results show good uniqueness, reliability, and uniformity with no occurrence of bit-aliasing. In particular, the reliability of the PUF is close to 100% over an environmental temperature range of 25 oC to 70 oC with ±10% variation in the supply voltage.

AB - Physical unclonable functions (PUFs), a new form of physical security primitive, enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs). Many PUF implementations have been proposed to generate these unique n-bit binary strings. However, they often offer insufficient uniqueness and reliability when implemented on FPGAs, and can consume excessive resources. To address these problems, in this paper we present an efficient, lightweight and scalable PUF identification (ID) generator circuit that offers a compact design with good uniqueness and reliability properties, and is specifically designed for FPGAs. A novel post-characterisation methodology is also proposed, which improves the reliability of a PUF without the need for any additional hardware resources. Moreover, the proposed postcharacterisation method can be generally used for any FPGA-based PUF designs. The PUF ID generator consumes 8.95% of the hardware resources of a low-cost Xilinx Spartan-6 LX9 FPGA and 0.81% of a Xilinx Artix-7 FPGA. Experimental results show good uniqueness, reliability, and uniformity with no occurrence of bit-aliasing. In particular, the reliability of the PUF is close to 100% over an environmental temperature range of 25 oC to 70 oC with ±10% variation in the supply voltage.

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