Improved Thermal Performance of SOI Using Compound Buried Layer

Paul Baine, John Montgomery, Mervyn Armstrong, Harold Gamble, Sarah J. Harrington, Sydney Nigrin, Robin Wilson, Kean B. Oo, Alastair Armstrong, Suli Suder

Research output: Contribution to conferencePaper

7 Citations (Scopus)
208 Downloads (Pure)

Abstract

The buried oxide (BOX) layer in silicon on insulator (SOI) was replaced by a compound buried layer (CBL) containing layers of SiO2, polycrystalline silicon (polysilicon), and SiO2. The undoped polysilicon in the CBL acted as a dielectric with a higher thermal conductivity than SiO2. CBL provides a reduced thermal resistance with the same equivalent oxide thickness as a standard SiO2 buried layer. Thermal resistance was further reduced by lateral heat flow through the polysilicon. Reduction in thermal resistance by up to 68% was observed, dependent on polysilicon thickness. CBL SOI substrates were designed and manufactured to achieve a 40% reduction in thermal resistance compared with an 1.0-μm SiO2 BOX. Power bipolar transistors with an active silicon layer thickness of 13.5 μm manufactured on CBL SOI substrates showed a 5%-17% reduction in thermal resistance compared with the standard SOI. This reduction was dependent on transistor layout geometry. Between 65% and 90% of the heat flow from these power transistors is laterally through the thick active silicon layer. Analysis confirmed that CBL SOI provided a 40% reduction in the vertical path thermal resistance. Devices employing thinner active silicon layers will achieve the greater benefit from reduction in vertical path thermal resistance offered by CBL SOI.
Original languageEnglish
Pages1999 - 2006
DOIs
Publication statusPublished - 14 May 2014

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