TY - JOUR
T1 - Inverse Class-E Amplifier With Transmission-Line Harmonic Suppression
AU - Thian, Mury
AU - Fusco, V.F.
PY - 2007/7
Y1 - 2007/7
N2 - This paper reports on the design methodology and experimental characterization of the inverse Class-E power amplifier. A demonstration amplifier with excellent second and third harmonic-suppression levels has been designed, constructed, and measured. The circuit fabricated using a 1.2-min gate-width GaAs MESFET is shown to be able to deliver 22-dBm output power at 2.3 GHz. The amplifier achieves a peak power-added efficiency of 64 % and drain efficiency of 69 %, and exhibits 11.6 dB power gain when operated from a 3-V supply voltage. Comparisons of simulated and measured results are given with good agreement between them being obtained. Experimental results are presented for the amplifier's response to Gaussian minimum shift keying modulation, where a peak error vector modulation value of 0.6% is measured.
AB - This paper reports on the design methodology and experimental characterization of the inverse Class-E power amplifier. A demonstration amplifier with excellent second and third harmonic-suppression levels has been designed, constructed, and measured. The circuit fabricated using a 1.2-min gate-width GaAs MESFET is shown to be able to deliver 22-dBm output power at 2.3 GHz. The amplifier achieves a peak power-added efficiency of 64 % and drain efficiency of 69 %, and exhibits 11.6 dB power gain when operated from a 3-V supply voltage. Comparisons of simulated and measured results are given with good agreement between them being obtained. Experimental results are presented for the amplifier's response to Gaussian minimum shift keying modulation, where a peak error vector modulation value of 0.6% is measured.
UR - http://www.scopus.com/inward/record.url?scp=34547114997&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2007.899617
DO - 10.1109/TCSI.2007.899617
M3 - Article
VL - 54
SP - 1555
EP - 1561
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
SN - 1057-7122
IS - 7
ER -