IPPro: FPGA based Image Processing Processor

Fahad Manzoor Siddiqui, Matthew Russell, Burak Bardak, Roger Woods, Karen Rafferty

Research output: Contribution to conferencePaperpeer-review

12 Citations (Scopus)
1429 Downloads (Pure)

Abstract

The paper presents IPPro which is a high performance, scalable soft-core processor targeted for image processing applications. It has been based on the Xilinx DSP48E1 architecture using the ZYNQ Field Programmable Gate Array and is a scalar 16-bit RISC processor that operates at 526MHz, giving 526MIPS of performance. Each IPPro core uses 1 DSP48, 1 Block RAM and 330 Kintex-7 slice-registers, thus making the processor as compact as possible whilst maintaining flexibility and programmability. A key aspect of the approach is in reducing the application design time and implementation effort by using multiple IPPro processors in a SIMD mode. For different applications, this allows us to exploit different levels of parallelism and mapping for the specified processing architecture with the supported instruction set. In this context, a Traffic Sign Recognition (TSR) algorithm has been prototyped on a Zedboard with the colour and morphology operations accelerated using multiple IPPros. Simulation and experimental results demonstrate that the processing platform is able to achieve a speedup of 15 to 33 times for colour filtering and morphology operations respectively, with a reduced design effort and time.
Original languageEnglish
Publication statusPublished - 20 Oct 2014
EventIEEE International Workshop on Signal Processing Systems - Belfast, United Kingdom
Duration: 20 Oct 201422 Oct 2014

Conference

ConferenceIEEE International Workshop on Signal Processing Systems
CountryUnited Kingdom
CityBelfast
Period20/10/201422/10/2014

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