JPEG encoder system-on-a-chip demonstrator

J.K. Hunter, J.V. McCanny, A. Simpson, Y. Hu, J.G. Doherty

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)


The design of a System-on-a-Chip (SoC) demonstrator for a baseline JPEG encoder core is presented. This combines a highly optimized Discrete Cosine Transform (DCT) and quantization unit with an entropy coder which has been realized using off-the-shelf synthesizable IP cores (Run-length coder, Huffman coder and data packer). When synthesized in a 0.35 µm CMOS process, the core can operate at speeds up to 100 MHz and contains 50 k gates plus 11.5 kbits of RAM. This is approximately 20% less than similar JPEG encoder designs reported in literature. When targeted at FPGA the core can operate up to 30 MHz and is capable of compressing 9-bit full-frame color input data at NTSC or PAL rates.
Original languageEnglish
Pages (from-to)762-766
Number of pages5
JournalConference Record of the Asilomar Conference on Signals, Systems and Computers
Publication statusPublished - 01 Jan 1999

Bibliographical note

Copyright 2004 Elsevier Science B.V., Amsterdam. All rights reserved.

ASJC Scopus subject areas

  • Hardware and Architecture
  • Signal Processing
  • Electrical and Electronic Engineering


Dive into the research topics of 'JPEG encoder system-on-a-chip demonstrator'. Together they form a unique fingerprint.

Cite this