Junctionless 6T SRAM cell

A. Kranti; C.-W. Lee; I. Ferain; R. Yan; N. Akhavan; P. Razavi; R. Yu; G. A. Armstrong; J.-P. Colinge

doi:10.1049/el.2010.2736

Junctionless 6T SRAM cell

A. Kranti, C.-W. Lee, I. Ferain, R. Yan, N. Akhavan, P. Razavi, R. Yu, G. A. Armstrong, J.-P. Colinge

School of Electronics, Electrical Engineering and Computer Science

Research output: Contribution to journal › Article › peer-review

49 Citations (Scopus)

226 Downloads (Pure)

Abstract

The design of a 6T SRAM cell with 20 nm junctionless (JL) MOSFETs is reported. It is shown that a 6T SRAM cell designed with JL MOSFETs achieves a high static noise margin (SNM) of 185 mV, retention noise or hold margin (RNM) of 381 mV and writability current (I_WR) of 33 µA along with a low leakage current (I_LEAK) of 2 pA at a supply voltage (V_DD) of 0.9 V for cell and pull-up ratios of 1. Results offer a new opportunity to design future SRAM cells with nanoscale JL MOSFETs.

Original language	English
Pages (from-to)	1491-1493
Journal	Electronics Letters
Volume	46
Issue number	22
DOIs	https://doi.org/10.1049/el.2010.2736
Publication status	Published - 28 Oct 2010

ASJC Scopus subject areas

Electrical and Electronic Engineering

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@article{cf47162cde6f4392abf352dff121dcab,

title = "Junctionless 6T SRAM cell",

abstract = "The design of a 6T SRAM cell with 20 nm junctionless (JL) MOSFETs is reported. It is shown that a 6T SRAM cell designed with JL MOSFETs achieves a high static noise margin (SNM) of 185 mV, retention noise or hold margin (RNM) of 381 mV and writability current (IWR) of 33 µA along with a low leakage current (ILEAK) of 2 pA at a supply voltage (VDD) of 0.9 V for cell and pull-up ratios of 1. Results offer a new opportunity to design future SRAM cells with nanoscale JL MOSFETs.",

author = "A. Kranti and C.-W. Lee and I. Ferain and R. Yan and N. Akhavan and P. Razavi and R. Yu and Armstrong, {G. A.} and J.-P. Colinge",

year = "2010",

month = oct,

day = "28",

doi = "10.1049/el.2010.2736",

language = "English",

volume = "46",

pages = "1491--1493",

journal = "Electronics Letters",

issn = "0013-5194",

publisher = "John Wiley & Sons Inc.",

number = "22",

}

TY - JOUR

T1 - Junctionless 6T SRAM cell

AU - Kranti, A.

AU - Lee, C.-W.

AU - Ferain, I.

AU - Yan, R.

AU - Akhavan, N.

AU - Razavi, P.

AU - Yu, R.

AU - Armstrong, G. A.

AU - Colinge, J.-P.

PY - 2010/10/28

Y1 - 2010/10/28

N2 - The design of a 6T SRAM cell with 20 nm junctionless (JL) MOSFETs is reported. It is shown that a 6T SRAM cell designed with JL MOSFETs achieves a high static noise margin (SNM) of 185 mV, retention noise or hold margin (RNM) of 381 mV and writability current (IWR) of 33 µA along with a low leakage current (ILEAK) of 2 pA at a supply voltage (VDD) of 0.9 V for cell and pull-up ratios of 1. Results offer a new opportunity to design future SRAM cells with nanoscale JL MOSFETs.

AB - The design of a 6T SRAM cell with 20 nm junctionless (JL) MOSFETs is reported. It is shown that a 6T SRAM cell designed with JL MOSFETs achieves a high static noise margin (SNM) of 185 mV, retention noise or hold margin (RNM) of 381 mV and writability current (IWR) of 33 µA along with a low leakage current (ILEAK) of 2 pA at a supply voltage (VDD) of 0.9 V for cell and pull-up ratios of 1. Results offer a new opportunity to design future SRAM cells with nanoscale JL MOSFETs.

U2 - 10.1049/el.2010.2736

DO - 10.1049/el.2010.2736

M3 - Article

SN - 0013-5194

VL - 46

SP - 1491

EP - 1493

JO - Electronics Letters

JF - Electronics Letters

IS - 22

ER -

Junctionless 6T SRAM cell

Abstract

ASJC Scopus subject areas

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