Lightweight hardware implementation of R-LWE lattice-based cryptography

Sailong Fan; Weiqiang Liu; James Howe; Ayesha Khalid; Maire O'Neill

doi:10.1109/APCCAS.2018.8605630

Lightweight hardware implementation of R-LWE lattice-based cryptography

Sailong Fan, Weiqiang Liu, James Howe, Ayesha Khalid, Maire O'Neill

School of Electronics, Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

18 Citations (Scopus)

578 Downloads (Pure)

Abstract

Lattice based cryptography (LBC) is one of the most promising post-quantum cryptographic candidates. Ringlearning with errors (R-LWE) is an encryption scheme of LBC. In this paper, a lightweight hardware implementation is presented including key generation, encryption, and decryption. The RLWE encryption scheme consists of a Gaussian sampler and polynomial multiplication. This paper uses cumulative distribution table (CDT) as the Gaussian sampler and schoolbook approach for the polynomial multiplication. The purpose of this architecture is to achieve small area consumption with high frequency. The hardware implementation results on the Xilinx Kintex-7 FPGA shows that the design consumes 808 slices and the frequency can be up to 288.35MHz.

Original language	English
Title of host publication	IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2018: Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	403-406
Number of pages	4
ISBN (Electronic)	9781538682401
ISBN (Print)	9781538682418
DOIs	https://doi.org/10.1109/APCCAS.2018.8605630
Publication status	Published - 10 Jan 2019
Event	14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 - Chengdu, China Duration: 26 Oct 2018 → 30 Oct 2018

Publication series

Name	IEEE Asia Pacific Conference on Circuits and Systems (APCCAS): Proceedings

Conference

Conference	14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018
Country/Territory	China
City	Chengdu
Period	26/10/2018 → 30/10/2018

Bibliographical note

Funding Information:
V. CONCLUSIONS In this work, a lightweight R-LWE hardware implementation is presented. The proposed design uses CDT as the Gaussian sampler and a schoolbook multiplier for polynomial multiplication. The design achieves the highest frequency with rather low hardware cost, compared with previous works. ACKNOWLEDGMENT This has been supported by NSFC (61871216) and Six Talent Peaks Project of Jiangsu Province (XYDXX-009).

Publisher Copyright:
© 2018 IEEE.

Keywords

cumulative distribution table
FPGA
lattice-based cryptography
polynomial multiplication
ring-learning with errors

ASJC Scopus subject areas

Biomedical Engineering
Electrical and Electronic Engineering
Instrumentation

Access to Document

10.1109/APCCAS.2018.8605630Licence: Unspecified

Lightweight Hardware Implementation of R-LWE Lattice-Based Cryptography
Copyright 2016 IEEE. This work is made available online in accordance with the publisher’s policies. Please refer to any applicable terms of use of the publisher.
Accepted author manuscript, 345 KBLicence: Unspecified

Cite this

Fan, S., Liu, W., Howe, J., Khalid, A., & O'Neill, M. (2019). Lightweight hardware implementation of R-LWE lattice-based cryptography. In IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2018: Proceedings (pp. 403-406). Article 8605630 (IEEE Asia Pacific Conference on Circuits and Systems (APCCAS): Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2018.8605630

@inproceedings{c4802c96f99744d7b0871736574e3362,

title = "Lightweight hardware implementation of R-LWE lattice-based cryptography",

abstract = "Lattice based cryptography (LBC) is one of the most promising post-quantum cryptographic candidates. Ringlearning with errors (R-LWE) is an encryption scheme of LBC. In this paper, a lightweight hardware implementation is presented including key generation, encryption, and decryption. The RLWE encryption scheme consists of a Gaussian sampler and polynomial multiplication. This paper uses cumulative distribution table (CDT) as the Gaussian sampler and schoolbook approach for the polynomial multiplication. The purpose of this architecture is to achieve small area consumption with high frequency. The hardware implementation results on the Xilinx Kintex-7 FPGA shows that the design consumes 808 slices and the frequency can be up to 288.35MHz.",

keywords = "cumulative distribution table, FPGA, lattice-based cryptography, polynomial multiplication, ring-learning with errors",

author = "Sailong Fan and Weiqiang Liu and James Howe and Ayesha Khalid and Maire O'Neill",

note = "Funding Information: V. CONCLUSIONS In this work, a lightweight R-LWE hardware implementation is presented. The proposed design uses CDT as the Gaussian sampler and a schoolbook multiplier for polynomial multiplication. The design achieves the highest frequency with rather low hardware cost, compared with previous works. ACKNOWLEDGMENT This has been supported by NSFC (61871216) and Six Talent Peaks Project of Jiangsu Province (XYDXX-009). Publisher Copyright: {\textcopyright} 2018 IEEE.; 14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 ; Conference date: 26-10-2018 Through 30-10-2018",

year = "2019",

month = jan,

day = "10",

doi = "10.1109/APCCAS.2018.8605630",

language = "English",

isbn = "9781538682418",

series = "IEEE Asia Pacific Conference on Circuits and Systems (APCCAS): Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "403--406",

booktitle = "IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2018: Proceedings",

address = "United States",

}

Fan, S, Liu, W, Howe, J, Khalid, A & O'Neill, M 2019, Lightweight hardware implementation of R-LWE lattice-based cryptography. in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2018: Proceedings., 8605630, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS): Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 403-406, 14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, 26/10/2018. https://doi.org/10.1109/APCCAS.2018.8605630

Lightweight hardware implementation of R-LWE lattice-based cryptography. / Fan, Sailong; Liu, Weiqiang; Howe, James et al.
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2018: Proceedings. Institute of Electrical and Electronics Engineers Inc., 2019. p. 403-406 8605630 (IEEE Asia Pacific Conference on Circuits and Systems (APCCAS): Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Lightweight hardware implementation of R-LWE lattice-based cryptography

AU - Fan, Sailong

AU - Liu, Weiqiang

AU - Howe, James

AU - Khalid, Ayesha

AU - O'Neill, Maire

N1 - Funding Information: V. CONCLUSIONS In this work, a lightweight R-LWE hardware implementation is presented. The proposed design uses CDT as the Gaussian sampler and a schoolbook multiplier for polynomial multiplication. The design achieves the highest frequency with rather low hardware cost, compared with previous works. ACKNOWLEDGMENT This has been supported by NSFC (61871216) and Six Talent Peaks Project of Jiangsu Province (XYDXX-009). Publisher Copyright: © 2018 IEEE.

PY - 2019/1/10

Y1 - 2019/1/10

N2 - Lattice based cryptography (LBC) is one of the most promising post-quantum cryptographic candidates. Ringlearning with errors (R-LWE) is an encryption scheme of LBC. In this paper, a lightweight hardware implementation is presented including key generation, encryption, and decryption. The RLWE encryption scheme consists of a Gaussian sampler and polynomial multiplication. This paper uses cumulative distribution table (CDT) as the Gaussian sampler and schoolbook approach for the polynomial multiplication. The purpose of this architecture is to achieve small area consumption with high frequency. The hardware implementation results on the Xilinx Kintex-7 FPGA shows that the design consumes 808 slices and the frequency can be up to 288.35MHz.

AB - Lattice based cryptography (LBC) is one of the most promising post-quantum cryptographic candidates. Ringlearning with errors (R-LWE) is an encryption scheme of LBC. In this paper, a lightweight hardware implementation is presented including key generation, encryption, and decryption. The RLWE encryption scheme consists of a Gaussian sampler and polynomial multiplication. This paper uses cumulative distribution table (CDT) as the Gaussian sampler and schoolbook approach for the polynomial multiplication. The purpose of this architecture is to achieve small area consumption with high frequency. The hardware implementation results on the Xilinx Kintex-7 FPGA shows that the design consumes 808 slices and the frequency can be up to 288.35MHz.

KW - cumulative distribution table

KW - FPGA

KW - lattice-based cryptography

KW - polynomial multiplication

KW - ring-learning with errors

U2 - 10.1109/APCCAS.2018.8605630

DO - 10.1109/APCCAS.2018.8605630

M3 - Conference contribution

AN - SCOPUS:85062230580

SN - 9781538682418

T3 - IEEE Asia Pacific Conference on Circuits and Systems (APCCAS): Proceedings

SP - 403

EP - 406

BT - IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2018: Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018

Y2 - 26 October 2018 through 30 October 2018

ER -

Fan S, Liu W, Howe J, Khalid A, O'Neill M. Lightweight hardware implementation of R-LWE lattice-based cryptography. In IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) 2018: Proceedings. Institute of Electrical and Electronics Engineers Inc. 2019. p. 403-406. 8605630. (IEEE Asia Pacific Conference on Circuits and Systems (APCCAS): Proceedings). doi: 10.1109/APCCAS.2018.8605630

Lightweight hardware implementation of R-LWE lattice-based cryptography

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

Access to Document

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Cite this