This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.
|Number of pages||15|
|Journal||Journal of VLSI signal processing systems for signal, image and video technology|
|Publication status||Published - 2000|
ASJC Scopus subject areas
- Information Systems
- Signal Processing
- Electrical and Electronic Engineering