Linear QR architecture for a single chip adaptive beamformer

G. Lightbody, R. Walke, Roger Woods, John McCanny

Research output: Contribution to journalArticlepeer-review

23 Citations (Scopus)


This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.
Original languageEnglish
Pages (from-to)67-81
Number of pages15
JournalJournal of VLSI signal processing systems for signal, image and video technology
Issue number1
Publication statusPublished - 2000

ASJC Scopus subject areas

  • Information Systems
  • Signal Processing
  • Electrical and Electronic Engineering


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