Abstract
PUF is a security primitive that exploits the fact that no two ICs are exactly the same. To verify a new PUF design, several metrics including uniqueness, reliability, and randomness must be evaluated, which requires various resources and a long set-up time. In this live demonstration, we have developed an automatically evaluation platform for the PUF design. To the authors' best knowledge, this is the first automatic evaluation platform for the PUF test. The evaluation platform can be used for both FPGA and ASCI PUF testing.
Original language | English |
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Title of host publication | Proceedings of 2016 IEEE International Symposium on Circuits and Systems (ISCAS) |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 2377 |
Number of pages | 1 |
ISBN (Electronic) | 9781479953400 |
ISBN (Print) | 9781479953417/16 |
DOIs | |
Publication status | Published - 11 Aug 2016 |
Event | 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada Duration: 22 May 2016 → 25 May 2016 |
Conference
Conference | 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 |
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Country/Territory | Canada |
City | Montreal |
Period | 22/05/2016 → 25/05/2016 |
Keywords
- evaluation platform
- FPGA
- PUF
ASJC Scopus subject areas
- Electrical and Electronic Engineering