Low power design of signal processing systems using characterization of silicon IP cores

G. Keane, J. R. Spanier, R. Woods

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Systems will rely increasingly on the effective and efficient use of pre-designed intellectual property (IP) cores. Power consumption, unlike speed and area, is much more difficult to predict at a higher level due to its reliance an the circuit level layout. This paper presents a characterization of multiplier blocks for an IP design flow. The paper shows how the blocks vary with respect to operating speed, wordlength and target application. It is shown using the design of a two dimensional discrete cosine transform (DCT), how IP component selection effects circuit power consumption.

Original languageEnglish
Title of host publicationConference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers
EditorsMichael B. Matthews
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages767-771
Number of pages5
Volume1
ISBN (Electronic)0780357000, 9780780357006
DOIs
Publication statusPublished - 01 Jan 1999
Externally publishedYes
Event33rd Asilomar Conference on Signals, Systems, and Computers, ACSSC 1999 - Pacific Grove, United States
Duration: 24 Oct 199927 Oct 1999

Conference

Conference33rd Asilomar Conference on Signals, Systems, and Computers, ACSSC 1999
CountryUnited States
CityPacific Grove
Period24/10/199927/10/1999

ASJC Scopus subject areas

  • Signal Processing
  • Computer Networks and Communications

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  • Cite this

    Keane, G., Spanier, J. R., & Woods, R. (1999). Low power design of signal processing systems using characterization of silicon IP cores. In M. B. Matthews (Ed.), Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers (Vol. 1, pp. 767-771). [832432] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ACSSC.1999.832432