Low power design of signal processing systems using characterization of silicon IP cores

G. Keane; J. R. Spanier; R. Woods

doi:10.1109/ACSSC.1999.832432

Low power design of signal processing systems using characterization of silicon IP cores

G. Keane, J. R. Spanier, R. Woods

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

Systems will rely increasingly on the effective and efficient use of pre-designed intellectual property (IP) cores. Power consumption, unlike speed and area, is much more difficult to predict at a higher level due to its reliance an the circuit level layout. This paper presents a characterization of multiplier blocks for an IP design flow. The paper shows how the blocks vary with respect to operating speed, wordlength and target application. It is shown using the design of a two dimensional discrete cosine transform (DCT), how IP component selection effects circuit power consumption.

Original language	English
Title of host publication	Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers
Editors	Michael B. Matthews
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	767-771
Number of pages	5
Volume	1
ISBN (Electronic)	0780357000, 9780780357006
DOIs	https://doi.org/10.1109/ACSSC.1999.832432
Publication status	Published - 01 Jan 1999
Externally published	Yes
Event	33rd Asilomar Conference on Signals, Systems, and Computers, ACSSC 1999 - Pacific Grove, United States Duration: 24 Oct 1999 → 27 Oct 1999

Conference

Conference	33rd Asilomar Conference on Signals, Systems, and Computers, ACSSC 1999
Country/Territory	United States
City	Pacific Grove
Period	24/10/1999 → 27/10/1999

ASJC Scopus subject areas

Signal Processing
Computer Networks and Communications

Access to Document

10.1109/ACSSC.1999.832432

Cite this

Keane, G., Spanier, J. R., & Woods, R. (1999). Low power design of signal processing systems using characterization of silicon IP cores. In M. B. Matthews (Ed.), Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers (Vol. 1, pp. 767-771). Article 832432 Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ACSSC.1999.832432

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title = "Low power design of signal processing systems using characterization of silicon IP cores",

abstract = "Systems will rely increasingly on the effective and efficient use of pre-designed intellectual property (IP) cores. Power consumption, unlike speed and area, is much more difficult to predict at a higher level due to its reliance an the circuit level layout. This paper presents a characterization of multiplier blocks for an IP design flow. The paper shows how the blocks vary with respect to operating speed, wordlength and target application. It is shown using the design of a two dimensional discrete cosine transform (DCT), how IP component selection effects circuit power consumption.",

author = "G. Keane and Spanier, {J. R.} and R. Woods",

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Keane, G, Spanier, JR & Woods, R 1999, Low power design of signal processing systems using characterization of silicon IP cores. in MB Matthews (ed.), Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers. vol. 1, 832432, Institute of Electrical and Electronics Engineers Inc., pp. 767-771, 33rd Asilomar Conference on Signals, Systems, and Computers, ACSSC 1999, Pacific Grove, United States, 24/10/1999. https://doi.org/10.1109/ACSSC.1999.832432

Low power design of signal processing systems using characterization of silicon IP cores. / Keane, G.; Spanier, J. R.; Woods, R.
Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers. ed. / Michael B. Matthews. Vol. 1 Institute of Electrical and Electronics Engineers Inc., 1999. p. 767-771 832432.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - Low power design of signal processing systems using characterization of silicon IP cores

AU - Keane, G.

AU - Spanier, J. R.

AU - Woods, R.

PY - 1999/1/1

Y1 - 1999/1/1

N2 - Systems will rely increasingly on the effective and efficient use of pre-designed intellectual property (IP) cores. Power consumption, unlike speed and area, is much more difficult to predict at a higher level due to its reliance an the circuit level layout. This paper presents a characterization of multiplier blocks for an IP design flow. The paper shows how the blocks vary with respect to operating speed, wordlength and target application. It is shown using the design of a two dimensional discrete cosine transform (DCT), how IP component selection effects circuit power consumption.

AB - Systems will rely increasingly on the effective and efficient use of pre-designed intellectual property (IP) cores. Power consumption, unlike speed and area, is much more difficult to predict at a higher level due to its reliance an the circuit level layout. This paper presents a characterization of multiplier blocks for an IP design flow. The paper shows how the blocks vary with respect to operating speed, wordlength and target application. It is shown using the design of a two dimensional discrete cosine transform (DCT), how IP component selection effects circuit power consumption.

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DO - 10.1109/ACSSC.1999.832432

M3 - Conference contribution

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VL - 1

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EP - 771

BT - Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers

A2 - Matthews, Michael B.

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 33rd Asilomar Conference on Signals, Systems, and Computers, ACSSC 1999

Y2 - 24 October 1999 through 27 October 1999

ER -

Low power design of signal processing systems using characterization of silicon IP cores

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ASJC Scopus subject areas

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