Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

S. McKeown, R. Woods*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

7 Citations (Scopus)
238 Downloads (Pure)

Abstract

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of36 and 37% over a Cooley–Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for aXilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh –Hadamard transforms.

Original languageEnglish
Pages (from-to)136-144
JournalIET Computers And Digital Techniques
Volume5
Issue number2
DOIs
Publication statusPublished - 01 Mar 2011

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

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