Low-Power Process-Variation Tolerant Arithmetic Units Using Input-Based Elastic Clocking

Debabrata Mohapatra*, Georgios Karakonstantis, Kaushik Roy

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

27 Citations (Scopus)

Abstract

In this paper we propose a design methodology for low-power high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in the fact that possible delay failures due to process variations and/or voltage scaling are predicted in advance and addressed by employing an elastic clocking technique. The prediction mechanism exploits the dependence of delay of arithmetic units upon input data patterns and identifies specific inputs that activate the critical path. Under iso-yield conditions, the proposed design operates at a lower scaled down Vdd without any performance degradation, while it ensures a superlative yield under a design style employing nominal supply and transistor threshold voltage. Simulation results show power savings of upto 29%, energy per computation savings of upto 25.5% and yield enhancement of upto 11.1% compared to the conventional adders and multipliers implemented in the 70nm BPTM technology. We incorporated the proposed modules in the execution unit of a five stage DLX pipeline to measure performance using SPEC2000 benchmarks [9]. Maximum area and throughput penalty obtained were 10% and 3% respectively.

Original languageEnglish
Title of host publicationISLPED'07: PROCEEDINGS OF THE 2007 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN
Place of PublicationNEW YORK
PublisherASSOC COMPUTING MACHINERY
Pages74-79
Number of pages6
ISBN (Print)978-1-59593-709-4
Publication statusPublished - 2007
Event12th International Symposium on Low Power Electronics and Design - Portland, United Kingdom
Duration: 27 Aug 200729 Aug 2007

Conference

Conference12th International Symposium on Low Power Electronics and Design
Country/TerritoryUnited Kingdom
Period27/08/200729/08/2007

Keywords

  • Low power
  • process tolerant
  • elastic clocking

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