Low-power systolic array processor architecture for FSBM video motion estimation

M. Jiang, Daniel Crookes, Stuart Davidson, Richard Turner

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.
Original languageEnglish
Pages (from-to)1146-1148
Number of pages3
JournalElectronics Letters
Issue number20
Publication statusPublished - 2006

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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