Low-power systolic array processor architecture for FSBM video motion estimation

M. Jiang; Daniel Crookes; Stuart Davidson; Richard Turner

doi:10.1049/el:20061972

Low-power systolic array processor architecture for FSBM video motion estimation

M. Jiang, Daniel Crookes, Stuart Davidson, Richard Turner

Research output: Contribution to journal › Article › peer-review

7 Citations (Scopus)

Abstract

A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.

Original language	English
Pages (from-to)	1146-1148
Number of pages	3
Journal	Electronics Letters
Volume	42
Issue number	20
DOIs	https://doi.org/10.1049/el:20061972
Publication status	Published - 2006

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el:20061972

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title = "Low-power systolic array processor architecture for FSBM video motion estimation",

abstract = "A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.",

author = "M. Jiang and Daniel Crookes and Stuart Davidson and Richard Turner",

year = "2006",

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AU - Crookes, Daniel

AU - Davidson, Stuart

AU - Turner, Richard

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AB - A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.

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U2 - 10.1049/el:20061972

DO - 10.1049/el:20061972

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SP - 1146

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JO - Electronics Letters

JF - Electronics Letters

IS - 20

ER -

Low-power systolic array processor architecture for FSBM video motion estimation

Abstract

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