TY - JOUR
T1 - MAPPING SYSTEM LEVEL FUNCTIONS ON TO BIT LEVEL SYSTOLIC ARRAYS.
AU - McCanny, J.V.
N1 - Copyright 2004 Elsevier B.V., All rights reserved.
PY - 1986/1/1
Y1 - 1986/1/1
N2 - Bit-level systolic-array structures for computing sums of products are studied in detail. It is shown that these can be subdivided into two classes and that within each class architectures can be described in terms of a set of constraint equations. It is further demonstrated that high-performance system-level functions with attractive VLSI properties can be constructed by matching data-flow geometries in bit-level and word-level architectures.
AB - Bit-level systolic-array structures for computing sums of products are studied in detail. It is shown that these can be subdivided into two classes and that within each class architectures can be described in terms of a set of constraint equations. It is further demonstrated that high-performance system-level functions with attractive VLSI properties can be constructed by matching data-flow geometries in bit-level and word-level architectures.
UR - http://www.scopus.com/inward/record.url?partnerID=yv4JPVwI&eid=2-s2.0-0022880817&md5=17731c20930781f8b861f9bb3ff23175
M3 - Article
AN - SCOPUS:0022880817
SN - 0736-7791
SP - 2159
EP - 2162
JO - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
JF - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
ER -