Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs

Konstantinos Tovletoglou; Lev Mukhanov; Georgios Karakonstantis; Athanasios Chatzidimitriou; George Papadimitriou; Manolis Kaliorakis; Dimitris Gizopoulos; Zacharias Hadjilambrou; Yiannakis Sazeides; Alejandro Lampropoulos; Shidhartha  Das; Phong Vo

doi:10.1109/DSN-W.2018.00013

Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs

Konstantinos Tovletoglou, Lev Mukhanov, Georgios Karakonstantis, Athanasios Chatzidimitriou, George Papadimitriou, Manolis Kaliorakis, Dimitris Gizopoulos, Zacharias Hadjilambrou, Yiannakis Sazeides, Alejandro Lampropoulos, Shidhartha Das, Phong Vo

School of Electronics, Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

312 Downloads (Pure)

Abstract

In this paper, we present the results of our comprehensive measurement study of the timing and voltage guardbands in memories and cores of a commodity ARMv8 based micro-server. Using various synthetic micro-benchmarks, we reveal how the adopted voltage margins vary among the 8 cores of the CPU chip, and among 3 different sigma chips and we show how prone they are to worst-case voltage noise. In addition, we characterize the variation of ‘weak’ DRAM cells in terms of their retention time across 72 DRAM chips and evaluate the error mitigation efficacy of the available error-correcting codes in case of operation under aggressively relaxed refresh periods. Finally, we show the overall energy savings that could be achieved by shaving the adopted guardbands in the cores and memories using various applications. Our characterization results show the potential to obtain up-to 38.8% energy savings in cores and up-to 27.3% within DRAMs.

Original language	English
Title of host publication	2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN): Proceedings
Pages	6-9
ISBN (Electronic)	978-1-5386-6553-4
DOIs	https://doi.org/10.1109/DSN-W.2018.00013
Publication status	Published - 23 Jul 2018
Event	IEEE/IFIP International Conference on Dependable Systems and Networks - Luxembourg, Luxembourg Duration: 25 Jun 2018 → 28 Jun 2018 Conference number: 48th

Publication series

Name
ISSN (Electronic)	2325-6664

Conference

Conference	IEEE/IFIP International Conference on Dependable Systems and Networks
Abbreviated title	DSN
Country/Territory	Luxembourg
City	Luxembourg
Period	25/06/2018 → 28/06/2018

Access to Document

10.1109/DSN-W.2018.00013Licence: Unspecified

Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs
© 2018 IEEE. This work is made available online in accordance with the publisher’s policies. Please refer to any applicable terms of use of the publisher.
Accepted author manuscript, 554 KBLicence: Unspecified

Cite this

Tovletoglou, K., Mukhanov, L., Karakonstantis, G., Chatzidimitriou, A., Papadimitriou, G., Kaliorakis, M., Gizopoulos, D., Hadjilambrou, Z., Sazeides, Y., Lampropoulos, A., Das, S., & Vo, P. (2018). Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs. In 2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN): Proceedings (pp. 6-9) https://doi.org/10.1109/DSN-W.2018.00013

Tovletoglou, Konstantinos ; Mukhanov, Lev ; Karakonstantis, Georgios ; Chatzidimitriou, Athanasios ; Papadimitriou, George ; Kaliorakis, Manolis ; Gizopoulos, Dimitris ; Hadjilambrou, Zacharias ; Sazeides, Yiannakis ; Lampropoulos, Alejandro ; Das, Shidhartha ; Vo, Phong. / Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs. 2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN): Proceedings. 2018. pp. 6-9

@inproceedings{547b2ecd21234436a1403287a149c95b,

title = "Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs",

abstract = "In this paper, we present the results of our comprehensive measurement study of the timing and voltage guardbands in memories and cores of a commodity ARMv8 based micro-server. Using various synthetic micro-benchmarks, we reveal how the adopted voltage margins vary among the 8 cores of the CPU chip, and among 3 different sigma chips and we show how prone they are to worst-case voltage noise. In addition, we characterize the variation of {\textquoteleft}weak{\textquoteright} DRAM cells in terms of their retention time across 72 DRAM chips and evaluate the error mitigation efficacy of the available error-correcting codes in case of operation under aggressively relaxed refresh periods. Finally, we show the overall energy savings that could be achieved by shaving the adopted guardbands in the cores and memories using various applications. Our characterization results show the potential to obtain up-to 38.8% energy savings in cores and up-to 27.3% within DRAMs. ",

author = "Konstantinos Tovletoglou and Lev Mukhanov and Georgios Karakonstantis and Athanasios Chatzidimitriou and George Papadimitriou and Manolis Kaliorakis and Dimitris Gizopoulos and Zacharias Hadjilambrou and Yiannakis Sazeides and Alejandro Lampropoulos and Shidhartha Das and Phong Vo",

year = "2018",

month = jul,

day = "23",

doi = "10.1109/DSN-W.2018.00013",

language = "English",

pages = "6--9",

booktitle = "2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN): Proceedings",

note = "IEEE/IFIP International Conference on Dependable Systems and Networks, DSN ; Conference date: 25-06-2018 Through 28-06-2018",

}

Tovletoglou, K, Mukhanov, L , Karakonstantis, G, Chatzidimitriou, A, Papadimitriou, G, Kaliorakis, M, Gizopoulos, D, Hadjilambrou, Z, Sazeides, Y, Lampropoulos, A, Das, S & Vo, P 2018, Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs. in 2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN): Proceedings. pp. 6-9, IEEE/IFIP International Conference on Dependable Systems and Networks, Luxembourg, Luxembourg, 25/06/2018. https://doi.org/10.1109/DSN-W.2018.00013

Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs. / Tovletoglou, Konstantinos; Mukhanov, Lev ; Karakonstantis, Georgios; Chatzidimitriou, Athanasios; Papadimitriou, George; Kaliorakis, Manolis; Gizopoulos, Dimitris; Hadjilambrou, Zacharias; Sazeides, Yiannakis; Lampropoulos, Alejandro; Das, Shidhartha ; Vo, Phong.

2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN): Proceedings. 2018. p. 6-9.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs

AU - Tovletoglou, Konstantinos

AU - Mukhanov, Lev

AU - Karakonstantis, Georgios

AU - Chatzidimitriou, Athanasios

AU - Papadimitriou, George

AU - Kaliorakis, Manolis

AU - Gizopoulos, Dimitris

AU - Hadjilambrou, Zacharias

AU - Sazeides, Yiannakis

AU - Lampropoulos, Alejandro

AU - Das, Shidhartha

AU - Vo, Phong

N1 - Conference code: 48th

PY - 2018/7/23

Y1 - 2018/7/23

N2 - In this paper, we present the results of our comprehensive measurement study of the timing and voltage guardbands in memories and cores of a commodity ARMv8 based micro-server. Using various synthetic micro-benchmarks, we reveal how the adopted voltage margins vary among the 8 cores of the CPU chip, and among 3 different sigma chips and we show how prone they are to worst-case voltage noise. In addition, we characterize the variation of ‘weak’ DRAM cells in terms of their retention time across 72 DRAM chips and evaluate the error mitigation efficacy of the available error-correcting codes in case of operation under aggressively relaxed refresh periods. Finally, we show the overall energy savings that could be achieved by shaving the adopted guardbands in the cores and memories using various applications. Our characterization results show the potential to obtain up-to 38.8% energy savings in cores and up-to 27.3% within DRAMs.

AB - In this paper, we present the results of our comprehensive measurement study of the timing and voltage guardbands in memories and cores of a commodity ARMv8 based micro-server. Using various synthetic micro-benchmarks, we reveal how the adopted voltage margins vary among the 8 cores of the CPU chip, and among 3 different sigma chips and we show how prone they are to worst-case voltage noise. In addition, we characterize the variation of ‘weak’ DRAM cells in terms of their retention time across 72 DRAM chips and evaluate the error mitigation efficacy of the available error-correcting codes in case of operation under aggressively relaxed refresh periods. Finally, we show the overall energy savings that could be achieved by shaving the adopted guardbands in the cores and memories using various applications. Our characterization results show the potential to obtain up-to 38.8% energy savings in cores and up-to 27.3% within DRAMs.

U2 - 10.1109/DSN-W.2018.00013

DO - 10.1109/DSN-W.2018.00013

M3 - Conference contribution

SP - 6

EP - 9

BT - 2018 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN): Proceedings

T2 - IEEE/IFIP International Conference on Dependable Systems and Networks

Y2 - 25 June 2018 through 28 June 2018

ER -

Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs

Abstract

Publication series

Conference

Access to Document

Fingerprint

Cite this