Memory-Centric Hardware Synthesis from Dataflow Models

Scott Fischaber, John McAllister, Roger Woods (Editor)

Research output: Chapter in Book/Report/Conference proceedingChapter

1 Citation (Scopus)

Abstract

Generation of hardware architectures directly from dataflow representations is increasingly being considered as research moves toward system level design methodologies. Creation of networks of IP cores to implement actor functionality is a common approach to the problem, but often the memory sub-systems produced using these techniques are inefficiently utilised. This paper explores some of the issues in terms of memory organisation and accesses when developing systems from these high level representations. Using a template matching design study, challenges such as modelling memory reuse and minimising buffer requirements are examined, yielding results with significantly less memory requirements and costly off-chip memory accesses.
Original languageEnglish
Title of host publicationEmbedded Computer Systems: Architectures, Modeling, and Simulation
Pages197-206
Number of pages10
DOIs
Publication statusPublished - Jul 2008
Event2008 International Workshop on Embedded Computer Systems: Architectures, Modelling and Simulation (SAMOS VIII) - Samos, Greece
Duration: 21 Jul 200824 Jul 2008

Publication series

NameLecture Notes in Computer Science
PublisherSpringer
Volume5114
ISSN (Electronic)0302-9743

Conference

Conference2008 International Workshop on Embedded Computer Systems: Architectures, Modelling and Simulation (SAMOS VIII)
CountryGreece
CitySamos
Period21/07/200824/07/2008

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  • Cite this

    Fischaber, S., McAllister, J., & Woods, R. (Ed.) (2008). Memory-Centric Hardware Synthesis from Dataflow Models. In Embedded Computer Systems: Architectures, Modeling, and Simulation (pp. 197-206). (Lecture Notes in Computer Science; Vol. 5114). https://doi.org/10.1007/978-3-540-70550-5_22