Microarchitecture-aware timing error prediction via deep neural networks

Nanometer circuits are becoming increasingly prone to timing errors due to worsening parametric variations and operation close to voltage and frequency limits. Such errors threaten the system functionality and make circuits increasingly vulnerable to fault injection attacks, thus escalating the need to accurately predict and avoid them. Recent studies focus on modelling these errors by exploiting various supervised Machine Learning (ML)-based techniques. However, such efforts have not yet explored Neural Network (NN) methods that could improve accuracy, while being more easily scalable to complex, deep-pipelined architectures. This is the first study to explore the application of NN models on the accurate prediction of timing errors while considering various microarchitecture and workload parameters. To enable this study, we utilized stochastic search-based techniques to generate error-prone microarchitecture-aware samples, even in operating regions where samples are limited, the large number of which is an essential requirement in deep learning modelling. Our novel framework combines post-layout dynamic timing analysis and genetic algorithms, considering the data-dependent path sensitization and instruction execution history. The generated samples are used to train and evaluate various NN models for timing error prediction under multiple operating conditions. To evaluate the high efficacy of the NN models, we tested them on 6 applications with more than 8.5M instruction sequences. Evaluation results show over 99.8% predictive accuracy, combined with up to a 121.35% increase (on average) of the true positive rate in real test data compared to prior studies.