The continuous scaling of transistor sizes and the increased static and dynamic parametric variations render nanometer circuits more prone to timing failures. To protect circuits from such failures, designers adopt pessimistic timing margins, which are estimated statically under rare worst-case conditions. In this paper, we aim at minimizing the timing failures, while avoiding such pessimistic margins by proposing an approach that initially minimizes the number of long latency paths within each processor pipeline stage and constrains them in as few stages as possible. Such an approach, not only reduces the timing failures, but also limits the potential error prone locations to only few pipeline registers/stages. To further reduce these failures, we exploit the path excitation dependence on data patterns and we truncate the bit-width of the operands in the few remaining long latency paths by setting a number of least significant bits to a constant value zero. Such truncation may incur quality loss, but this can be controlled by carefully selecting the number of truncated bits and will be in any case less than the catastrophic loss that may be incurred under random timing failures. Additionally, our framework performs post-place and route dynamic timing analysis based on real operands that are extracted from a variety of applications, helping to estimate the bit error rate, while considering the dynamic data dependent path excitation. When applied to an IEEE-754 compatible double precision Floating Point Unit (FPU), the proposed approach reduces the timing failures by 104.5x on average compared to a reference FPU design under an assumed 8.1% variation-induced worst-case path delay increase in a 45 nm process. Finally, results show that path shaping alone introduces an insignificant 0.25% area and 5.7% power overhead with no performance cost. The combination of path shaping with aggressive operand bit-width truncation leads to up-to 44.7% on average power savings due to the substantially reduced switching activity at a minimal quality loss.
|Title of host publication||2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018|
|Number of pages||6|
|Publication status||Published - 01 Oct 2018|
|Event||International Symposium on On-Line Testing and Robust System Design, IOLTS - Costa Brava, Spain|
Duration: 02 Jul 2018 → 04 Jul 2018
|Name||2018 IEEE 24th International Symposium on On-Line Testing and Robust System Design, IOLTS 2018|
|Conference||International Symposium on On-Line Testing and Robust System Design, IOLTS|
|Period||02/07/2018 → 04/07/2018|
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Cross-layer instruction-aware timing error mitigation & evaluation for energy-efficient dependable architecturesAuthor: Tsiokanos, I., Jul 2021
Student thesis: Doctoral Thesis › Doctor of Philosophy