Multi-Incentive Delay-based (MID) PUF

Zhengran Zhang, Chongyan Gu, Yijun Cui, Chuan Zhang, Maire O'Neill, Weiqiang Liu*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
18 Downloads (Pure)

Abstract

This paper proposes a new PUF, namely Multiincentive Delay-based PUF (MID PUF), which utilizes the fast carry logic (FCL) of Field Programmable Gate Arrays (FPGAs). The proposed MID PUF is completely and efficiently implemented in XOR gates of FCLs. Compared to other single signal excited PUF designs, e.g. Arbiter PUF, multiple excitations are applied on the same delay line to produce multiple outputs. To the authors’ best knowledge, this is the first strong PUF based on only FCLs. The proposed MID PUF is implemented on Xilinx Spartan-6 XC6SLX9 FPGAs and a reliability experiment is carried out under the operating temperature in a range of 0~70. The experimental results show that the proposed MID PUF has a high uniqueness and reliability performance, as well as low hardware consumption. Due to its advantages in both hardware efficiency and PUF metrics, the proposed MID PUF is promising for lowcost security applications on FPGAs.
Original languageEnglish
Title of host publication IEEE International Symposium on Circuits and Systems (ISCAS) 2019 26/05/2019 → 29/05/2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Volume2019-May
ISBN (Electronic)9781728103976
DOIs
Publication statusPublished - 2019
Event2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan
Duration: 26 May 201929 May 2019
https://www.iscas2019.org/

Conference

Conference2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
CountryJapan
CitySapporo
Period26/05/201929/05/2019
Internet address

Keywords

  • Low-cost
  • Multi-incentive
  • PUF
  • Reliability
  • Uniqueness

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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