New FFT architecture and chip design for motion compensation based on phase correlation

C.C.W. Hui, T.J. Ding, J.V. McCanny, R.F. Woods

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)


Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-rime video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.
Original languageEnglish
Title of host publicationIEEE Intl. Conf. on Application Specific Systems, Architectures and Processors, eds. J Fortes, C Mongeget, K Pahri and V Taylor, IEEE Computer Society Press, 1996
Number of pages10
ISBN (Electronic)ISBN 0-8186-7542-X
Publication statusPublished - 01 Jan 1996

Bibliographical note

Copyright 2004 Elsevier Science B.V., Amsterdam. All rights reserved.


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