Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-rime video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.
|Title of host publication||IEEE Intl. Conf. on Application Specific Systems, Architectures and Processors, eds. J Fortes, C Mongeget, K Pahri and V Taylor, IEEE Computer Society Press, 1996|
|Number of pages||10|
|ISBN (Electronic)||ISBN 0-8186-7542-X|
|Publication status||Published - 01 Jan 1996|
Bibliographical noteCopyright 2004 Elsevier Science B.V., Amsterdam. All rights reserved.
Hui, C. C. W., Ding, T. J., McCanny, J. V., & Woods, R. F. (1996). New FFT architecture and chip design for motion compensation based on phase correlation. In IEEE Intl. Conf. on Application Specific Systems, Architectures and Processors, eds. J Fortes, C Mongeget, K Pahri and V Taylor, IEEE Computer Society Press, 1996 (pp. 83-92)