New FFT architecture and chip design for motion compensation based on phase correlation

C.C.W. Hui; T.J. Ding; J.V. McCanny; R.F. Woods

New FFT architecture and chip design for motion compensation based on phase correlation

C.C.W. Hui
, T.J. Ding
, J.V. McCanny
, R.F. Woods

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-rime video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.

Original language	English
Title of host publication	IEEE Intl. Conf. on Application Specific Systems, Architectures and Processors, eds. J Fortes, C Mongeget, K Pahri and V Taylor, IEEE Computer Society Press, 1996
Pages	83-92
Number of pages	10
ISBN (Electronic)	ISBN 0-8186-7542-X
Publication status	Published - 01 Jan 1996

Bibliographical note

Cite this

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title = "New FFT architecture and chip design for motion compensation based on phase correlation",

abstract = "Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-rime video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.",

author = "C.C.W. Hui and T.J. Ding and J.V. McCanny and R.F. Woods",

year = "1996",

month = jan,

day = "1",

language = "English",

pages = "83--92",

booktitle = "IEEE Intl. Conf. on Application Specific Systems, Architectures and Processors, eds. J Fortes, C Mongeget, K Pahri and V Taylor, IEEE Computer Society Press, 1996",

}

New FFT architecture and chip design for motion compensation based on phase correlation. / Hui, C.C.W.; Ding, T.J.; McCanny, J.V. et al.
IEEE Intl. Conf. on Application Specific Systems, Architectures and Processors, eds. J Fortes, C Mongeget, K Pahri and V Taylor, IEEE Computer Society Press, 1996 . 1996. p. 83-92.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - New FFT architecture and chip design for motion compensation based on phase correlation

AU - Hui, C.C.W.

AU - Ding, T.J.

AU - McCanny, J.V.

AU - Woods, R.F.

PY - 1996/1/1

Y1 - 1996/1/1

N2 - Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-rime video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.

AB - Details of a new low power FFT processor for use in digital television applications are presented. This has been fabricated using a 0.6 µm CMOS technology and can perform a 64 point complex forward or inverse FFT on real-rime video at up to 18 Megasamples per second. It comprises 0.5 million transistors in a die area of 7.8×8 mm and dissipates 1 W. Its performance, in terms of computational rate per area per watt, is significantly higher than previously reported devices, leading to a cost-effective silicon solution for high quality video processing applications. This is the result of using a novel VLSI architecture which has been derived from a first principles factorisation of the DFT matrix and tailored to a direct silicon implementation.

UR - https://www.scopus.com/pages/publications/0029754519

M3 - Conference contribution

AN - SCOPUS:0029754519

SP - 83

EP - 92

BT - IEEE Intl. Conf. on Application Specific Systems, Architectures and Processors, eds. J Fortes, C Mongeget, K Pahri and V Taylor, IEEE Computer Society Press, 1996

ER -

New FFT architecture and chip design for motion compensation based on phase correlation

Abstract

Bibliographical note

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