Field programmable gate array (FPGA) technology is a powerful platform for implementing computationally complex, digital signal processing (DSP) systems. Applications that are multi-modal, however, are designed for worse case conditions. In this paper, genetic sequencing techniques are applied to give a more sophisticated decomposition of the algorithmic variations, thus allowing an unified hardware architecture which gives a 10-25% area saving and 15% power saving for a digital radar receiver.
|Title of host publication||2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors (ASAP)|
|Publisher||Institute of Electrical and Electronics Engineers (IEEE)|
|Pages||169 - 172|
|Number of pages||3|
|Publication status||Published - 12 Jul 2012|