Novel intrinsic physical unclonable function design for post-quantum cryptography

The hardware implementations of post-quantum cryptography (PQC) algorithms are vulnerable to fault injection attacks. As a hardware security primitive, the intrinsic physical unclonable function (PUF) is a possible countermeasure for these attacks with low resource overheads. In this work, a novel intrinsic PUF, frequency adjustable software PUF (FAS-PUF), is proposed to provide a device identification for PQC chips. The FAS-PUF is based on an inherent timing logic in the ring-learning with error (R-LWE) decryption circuit of PQC chips. The FAS-PUF uses a 256∗13∗3 -bit input ciphertext of the decryption circuit as a challenge, and uses a 256-bit decryption output as a response with an adjustable overclocking. Since the entropy of the FAS-PUF utilises the manifested timing errors caused by the overclocking, the FAS-PUF does not need to modify the existing hardware circuits, i.e. preserves the original circuit functions, which significantly reduces hardware resource consumption and power overhead. Meanwhile, to mitigate the affection of circuits' metastablities to PUF's stability under overclocking, a dynamic clock frequency selection method is used to determine the optimal frequency point for generating PUF responses. The proposed FAS-PUF is also a Strong PUF design with a significant number of Challenge/Response Pairs (CRPs) provided. The proposed design is implemented on Xilinx Basys3 FPGAs. The experimental results show that the FAS-PUF has a good uniqueness, uniformity and stability compared with other intrinsic PUFs.