Novel lightweight FF-APUF design for FPGA

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

Physical unclonable functions (PUFs), are a new type of physical security primitive which enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). Due to their flexibility and lower time to market, FPGAs are increasingly used for many applications. Arbiter PUFs (APUFs) are among the most widely studied PUF designs. However, they often suffer from poor uniqueness and reliability characteristics, are difficult to implement in FPGAs and consume excessive FPGA resources. To address these problems, a new Flip-flop based APUF (FF-APUF) design is proposed that offers a compact architecture, combined with strong uniqueness and good reliability. It is specifically designed for FPGAs. The proposed work is verified on a low-cost Nexys4 board based on the latest 28 nm technology Xilinx Artix-7 FPGA. The proposed FF-APUF circuit for generating a 1-bit response consumes only 44 slices, which is a saving of more than 66% in hardware resources over previous related research. Moreover, experimental results show improvements in both uniqueness and reliability. In particular, the expected uniqueness of the response bits is 40% on FPGA, which significantly improves upon a uniqueness of 9% achieved in previous work.

LanguageEnglish
Title of host publication29th IEEE International System on Chip Conference, SOCC 2016: Proceedings
PublisherIEEE Computer Society
Pages75-80
Number of pages6
ISBN (Electronic)9781509013661
DOIs
Publication statusPublished - 24 Apr 2017
Event29th IEEE International System on Chip Conference, SOCC 2016 - Seattle, United States
Duration: 06 Sep 201609 Sep 2016

Publication series

NameIEEE International System-on-Chip Conference (SOCC)
PublisherIEEE
ISSN (Electronic)2164-1706

Conference

Conference29th IEEE International System on Chip Conference, SOCC 2016
CountryUnited States
CitySeattle
Period06/09/201609/09/2016

Fingerprint

Flip flop circuits
Field programmable gate arrays (FPGA)
Application specific integrated circuits
Hardware
Networks (circuits)
Hardware security
Costs

Cite this

Gu, C., Cui, Y., Hanley, N., & O'Neill, M. (2017). Novel lightweight FF-APUF design for FPGA. In 29th IEEE International System on Chip Conference, SOCC 2016: Proceedings (pp. 75-80). [7905439] (IEEE International System-on-Chip Conference (SOCC)). IEEE Computer Society. https://doi.org/10.1109/SOCC.2016.7905439
Gu, Chongyan ; Cui, Yijun ; Hanley, Neil ; O'Neill, Maire. / Novel lightweight FF-APUF design for FPGA. 29th IEEE International System on Chip Conference, SOCC 2016: Proceedings. IEEE Computer Society, 2017. pp. 75-80 (IEEE International System-on-Chip Conference (SOCC)).
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abstract = "Physical unclonable functions (PUFs), are a new type of physical security primitive which enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). Due to their flexibility and lower time to market, FPGAs are increasingly used for many applications. Arbiter PUFs (APUFs) are among the most widely studied PUF designs. However, they often suffer from poor uniqueness and reliability characteristics, are difficult to implement in FPGAs and consume excessive FPGA resources. To address these problems, a new Flip-flop based APUF (FF-APUF) design is proposed that offers a compact architecture, combined with strong uniqueness and good reliability. It is specifically designed for FPGAs. The proposed work is verified on a low-cost Nexys4 board based on the latest 28 nm technology Xilinx Artix-7 FPGA. The proposed FF-APUF circuit for generating a 1-bit response consumes only 44 slices, which is a saving of more than 66{\%} in hardware resources over previous related research. Moreover, experimental results show improvements in both uniqueness and reliability. In particular, the expected uniqueness of the response bits is 40{\%} on FPGA, which significantly improves upon a uniqueness of 9{\%} achieved in previous work.",
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Gu, C, Cui, Y, Hanley, N & O'Neill, M 2017, Novel lightweight FF-APUF design for FPGA. in 29th IEEE International System on Chip Conference, SOCC 2016: Proceedings., 7905439, IEEE International System-on-Chip Conference (SOCC), IEEE Computer Society, pp. 75-80, 29th IEEE International System on Chip Conference, SOCC 2016, Seattle, United States, 06/09/2016. https://doi.org/10.1109/SOCC.2016.7905439

Novel lightweight FF-APUF design for FPGA. / Gu, Chongyan; Cui, Yijun; Hanley, Neil; O'Neill, Maire.

29th IEEE International System on Chip Conference, SOCC 2016: Proceedings. IEEE Computer Society, 2017. p. 75-80 7905439 (IEEE International System-on-Chip Conference (SOCC)).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Gu C, Cui Y, Hanley N, O'Neill M. Novel lightweight FF-APUF design for FPGA. In 29th IEEE International System on Chip Conference, SOCC 2016: Proceedings. IEEE Computer Society. 2017. p. 75-80. 7905439. (IEEE International System-on-Chip Conference (SOCC)). https://doi.org/10.1109/SOCC.2016.7905439