TY - GEN
T1 - Novel lightweight FF-APUF design for FPGA
AU - Gu, Chongyan
AU - Cui, Yijun
AU - Hanley, Neil
AU - O'Neill, Maire
PY - 2017/4/24
Y1 - 2017/4/24
N2 - Physical unclonable functions (PUFs), are a new type of physical security primitive which enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). Due to their flexibility and lower time to market, FPGAs are increasingly used for many applications. Arbiter PUFs (APUFs) are among the most widely studied PUF designs. However, they often suffer from poor uniqueness and reliability characteristics, are difficult to implement in FPGAs and consume excessive FPGA resources. To address these problems, a new Flip-flop based APUF (FF-APUF) design is proposed that offers a compact architecture, combined with strong uniqueness and good reliability. It is specifically designed for FPGAs. The proposed work is verified on a low-cost Nexys4 board based on the latest 28 nm technology Xilinx Artix-7 FPGA. The proposed FF-APUF circuit for generating a 1-bit response consumes only 44 slices, which is a saving of more than 66% in hardware resources over previous related research. Moreover, experimental results show improvements in both uniqueness and reliability. In particular, the expected uniqueness of the response bits is 40% on FPGA, which significantly improves upon a uniqueness of 9% achieved in previous work.
AB - Physical unclonable functions (PUFs), are a new type of physical security primitive which enable digital identifiers to be extracted from devices, such as field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). Due to their flexibility and lower time to market, FPGAs are increasingly used for many applications. Arbiter PUFs (APUFs) are among the most widely studied PUF designs. However, they often suffer from poor uniqueness and reliability characteristics, are difficult to implement in FPGAs and consume excessive FPGA resources. To address these problems, a new Flip-flop based APUF (FF-APUF) design is proposed that offers a compact architecture, combined with strong uniqueness and good reliability. It is specifically designed for FPGAs. The proposed work is verified on a low-cost Nexys4 board based on the latest 28 nm technology Xilinx Artix-7 FPGA. The proposed FF-APUF circuit for generating a 1-bit response consumes only 44 slices, which is a saving of more than 66% in hardware resources over previous related research. Moreover, experimental results show improvements in both uniqueness and reliability. In particular, the expected uniqueness of the response bits is 40% on FPGA, which significantly improves upon a uniqueness of 9% achieved in previous work.
UR - http://www.scopus.com/inward/record.url?scp=85019060989&partnerID=8YFLogxK
U2 - 10.1109/SOCC.2016.7905439
DO - 10.1109/SOCC.2016.7905439
M3 - Conference contribution
AN - SCOPUS:85019060989
T3 - IEEE International System-on-Chip Conference (SOCC)
SP - 75
EP - 80
BT - 29th IEEE International System on Chip Conference, SOCC 2016: Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 29th IEEE International System on Chip Conference, SOCC 2016
Y2 - 6 September 2016 through 9 September 2016
ER -