Novel mapping of a linear QR architecture

G. Lightbody; R. Walke; Roger Woods; John McCanny

doi:10.1109/ICASSP.1999.758303

Novel mapping of a linear QR architecture

G. Lightbody
, R. Walke
, Roger Woods
, John McCanny

School of Electronics, Electrical Engineering and Computer Science

Research output: Contribution to conference › Paper › peer-review

9 Citations (Scopus)

Abstract

This paper presents a novel architecture mapping technique which was essential in the design of a QR array which forms the core processor of a single chip adaptive beamforming system. The mapping technique assigns a QR triangular array of 2m2+3m+l cells down onto a linear architecture of m+l processors. The mapping results in a linear systolic architecture with one hundred percent hardware utilisation, local interconnects and individual processors for boundary and internal cell operations. In addition, this paper highlights the effect latency has on the validity of the linear architecture.

Original language	English
Pages	1933-1936
Number of pages	4
DOIs	https://doi.org/10.1109/ICASSP.1999.758303
Publication status	Published - 06 Aug 2002
Event	IEEE International Conference on Acoustics, Speech, and Signal Processing 1999 - Phoenix, United States Duration: 15 Mar 1999 → 19 Mar 1999 https://doi.org/10.1109/ICASSP.1999

Conference

Conference	IEEE International Conference on Acoustics, Speech, and Signal Processing 1999
Abbreviated title	ICASSP 1999
Country/Territory	United States
City	Phoenix
Period	15/03/1999 → 19/03/1999
Internet address	https://doi.org/10.1109/ICASSP.1999

ASJC Scopus subject areas

Software
Signal Processing
Electrical and Electronic Engineering

Access to Document

10.1109/ICASSP.1999.758303Licence: Unspecified

Cite this

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title = "Novel mapping of a linear QR architecture",

abstract = "This paper presents a novel architecture mapping technique which was essential in the design of a QR array which forms the core processor of a single chip adaptive beamforming system. The mapping technique assigns a QR triangular array of 2m2+3m+l cells down onto a linear architecture of m+l processors. The mapping results in a linear systolic architecture with one hundred percent hardware utilisation, local interconnects and individual processors for boundary and internal cell operations. In addition, this paper highlights the effect latency has on the validity of the linear architecture. ",

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AU - Woods, Roger

AU - McCanny, John

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N2 - This paper presents a novel architecture mapping technique which was essential in the design of a QR array which forms the core processor of a single chip adaptive beamforming system. The mapping technique assigns a QR triangular array of 2m2+3m+l cells down onto a linear architecture of m+l processors. The mapping results in a linear systolic architecture with one hundred percent hardware utilisation, local interconnects and individual processors for boundary and internal cell operations. In addition, this paper highlights the effect latency has on the validity of the linear architecture.

AB - This paper presents a novel architecture mapping technique which was essential in the design of a QR array which forms the core processor of a single chip adaptive beamforming system. The mapping technique assigns a QR triangular array of 2m2+3m+l cells down onto a linear architecture of m+l processors. The mapping results in a linear systolic architecture with one hundred percent hardware utilisation, local interconnects and individual processors for boundary and internal cell operations. In addition, this paper highlights the effect latency has on the validity of the linear architecture.

U2 - 10.1109/ICASSP.1999.758303

DO - 10.1109/ICASSP.1999.758303

M3 - Paper

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EP - 1936

T2 - IEEE International Conference on Acoustics, Speech, and Signal Processing 1999

Y2 - 15 March 1999 through 19 March 1999

ER -

Novel mapping of a linear QR architecture

Abstract

Conference

ASJC Scopus subject areas

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Cite this