NS-SRAM: neighborhood solidarity SRAM for reliability enhancement of SRAM memories

Ihsen Alouani, Hamzeh Ahangari, Ozcan Ozturk, Smail Niar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Technology shift and voltage scaling increased the susceptibility of Static Random Access Memories (SRAMs) to errors dramatically. In this paper, we present NS-SRAM, for Neighborhood Solidarity SRAM, a new technique to enhance error resilience of SRAMs by exploiting the adjacent memory bit data. Bit cells of a memory line are paired together in circuit level to mutually increase the static noise margin and critical charge of a cell. Unlike existing techniques, NS-SRAM aims to enhance both Bit Error Rate (BER) and Soft Error rate (SER) at the same time. Due to auto-adaptive joiners, each of the adjacent cells' nodes is connected to its counterpart in the neighbor bit. NS-SRAM enhances read-stability by increasing critical Read Static Noise Margin (RSNM), thereby decreasing faults when circuit operates under voltage scaling. It also increases hold-stability and critical charge to mitigate soft-errors. By the proposed technique, reliability of SRAM based structures such as cache memories and register files can drastically be improved with comparable area overhead to existing hardening techniques. Moreover it does not require any extra-memory, does not impact the memory effective size, and has no negative impact on performance.
Original languageEnglish
Title of host publication2016 Euromicro Conference on Digital System Design (DSD): Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages154-159
ISBN (Electronic)9781509028177
ISBN (Print)9781509028184
DOIs
Publication statusPublished - 27 Oct 2016
Externally publishedYes

Publication series

NameEuromicro Conference on Digital System Design (DSD): Proceedings

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