On the performance of LDPC and turbo decoder architectures with unreliable memories

Joao Andrade; Aida Vosoughi; Guohui Wang; Georgios Karakonstantis; Andreas Burg; Gabriel Falcao; Vitor Silva; Joseph R. Cavallaro

doi:10.1109/ACSSC.2014.7094504

On the performance of LDPC and turbo decoder architectures with unreliable memories

Joao Andrade, Aida Vosoughi, Guohui Wang, Georgios Karakonstantis, Andreas Burg, Gabriel Falcao, Vitor Silva, Joseph R. Cavallaro

School of Electronics, Electrical Engineering and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

In this paper, we investigate the impact of faulty memory bit-cells on the performance of LDPC and Turbo channel decoders based on realistic memory failure models. Our study investigates the inherent error resilience of such codes to potential memory faults affecting the decoding process. We develop two mitigation mechanisms that reduce the impact of memory faults rather than correcting every single error. We show how protection of only few bit-cells is sufficient to deal with high defect rates. In addition, we show how the use of repair-iterations specifically helps mitigating the impact of faults that occur inside the decoder itself.

Original language	English
Title of host publication	Conference Record - Asilomar Conference on Signals, Systems and Computers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	542-547
Number of pages	6
ISBN (Electronic)	9781479982974
ISBN (Print)	9781479982950, ISSN 1058-6393
DOIs	https://doi.org/10.1109/ACSSC.2014.7094504
Publication status	Published - 24 Apr 2015
Event	48th Asilomar Conference on Signals, Systems and Computers - Pacific Grove, United States Duration: 02 Nov 2014 → 05 Nov 2014

Conference

Conference	48th Asilomar Conference on Signals, Systems and Computers
Country/Territory	United States
City	Pacific Grove
Period	02/11/2014 → 05/11/2014

ASJC Scopus subject areas

Computer Networks and Communications
Signal Processing

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10.1109/ACSSC.2014.7094504

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Andrade, J., Vosoughi, A., Wang, G., Karakonstantis, G., Burg, A., Falcao, G., Silva, V., & Cavallaro, J. R. (2015). On the performance of LDPC and turbo decoder architectures with unreliable memories. In Conference Record - Asilomar Conference on Signals, Systems and Computers (pp. 542-547). Article 7094504 Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ACSSC.2014.7094504

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title = "On the performance of LDPC and turbo decoder architectures with unreliable memories",

abstract = "In this paper, we investigate the impact of faulty memory bit-cells on the performance of LDPC and Turbo channel decoders based on realistic memory failure models. Our study investigates the inherent error resilience of such codes to potential memory faults affecting the decoding process. We develop two mitigation mechanisms that reduce the impact of memory faults rather than correcting every single error. We show how protection of only few bit-cells is sufficient to deal with high defect rates. In addition, we show how the use of repair-iterations specifically helps mitigating the impact of faults that occur inside the decoder itself.",

author = "Joao Andrade and Aida Vosoughi and Guohui Wang and Georgios Karakonstantis and Andreas Burg and Gabriel Falcao and Vitor Silva and Cavallaro, {Joseph R.}",

year = "2015",

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doi = "10.1109/ACSSC.2014.7094504",

language = "English",

isbn = "9781479982950",

pages = "542--547",

booktitle = "Conference Record - Asilomar Conference on Signals, Systems and Computers",

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note = "48th Asilomar Conference on Signals, Systems and Computers ; Conference date: 02-11-2014 Through 05-11-2014",

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Andrade, J, Vosoughi, A, Wang, G, Karakonstantis, G, Burg, A, Falcao, G, Silva, V & Cavallaro, JR 2015, On the performance of LDPC and turbo decoder architectures with unreliable memories. in Conference Record - Asilomar Conference on Signals, Systems and Computers., 7094504, Institute of Electrical and Electronics Engineers Inc., pp. 542-547, 48th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, United States, 02/11/2014. https://doi.org/10.1109/ACSSC.2014.7094504

On the performance of LDPC and turbo decoder architectures with unreliable memories. / Andrade, Joao; Vosoughi, Aida; Wang, Guohui et al.
Conference Record - Asilomar Conference on Signals, Systems and Computers. Institute of Electrical and Electronics Engineers Inc., 2015. p. 542-547 7094504.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Falcao, Gabriel

AU - Silva, Vitor

AU - Cavallaro, Joseph R.

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AB - In this paper, we investigate the impact of faulty memory bit-cells on the performance of LDPC and Turbo channel decoders based on realistic memory failure models. Our study investigates the inherent error resilience of such codes to potential memory faults affecting the decoding process. We develop two mitigation mechanisms that reduce the impact of memory faults rather than correcting every single error. We show how protection of only few bit-cells is sufficient to deal with high defect rates. In addition, we show how the use of repair-iterations specifically helps mitigating the impact of faults that occur inside the decoder itself.

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BT - Conference Record - Asilomar Conference on Signals, Systems and Computers

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ER -

On the performance of LDPC and turbo decoder architectures with unreliable memories

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