On the performance of LDPC and turbo decoder architectures with unreliable memories

Joao Andrade, Aida Vosoughi, Guohui Wang, Georgios Karakonstantis, Andreas Burg, Gabriel Falcao, Vitor Silva, Joseph R. Cavallaro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

In this paper, we investigate the impact of faulty memory bit-cells on the performance of LDPC and Turbo channel decoders based on realistic memory failure models. Our study investigates the inherent error resilience of such codes to potential memory faults affecting the decoding process. We develop two mitigation mechanisms that reduce the impact of memory faults rather than correcting every single error. We show how protection of only few bit-cells is sufficient to deal with high defect rates. In addition, we show how the use of repair-iterations specifically helps mitigating the impact of faults that occur inside the decoder itself.

Original languageEnglish
Title of host publicationConference Record - Asilomar Conference on Signals, Systems and Computers
PublisherIEEE Computer Society
Pages542-547
Number of pages6
ISBN (Electronic)9781479982974
ISBN (Print)9781479982950, ISSN 1058-6393
DOIs
Publication statusPublished - 24 Apr 2015
Event48th Asilomar Conference on Signals, Systems and Computers - Pacific Grove, United States
Duration: 02 Nov 201405 Nov 2014

Conference

Conference48th Asilomar Conference on Signals, Systems and Computers
CountryUnited States
CityPacific Grove
Period02/11/201405/11/2014

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Signal Processing

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