One word/cycle HC-128 accelerator via state-splitting optimization

Ayesha Khalid, Prasanna Ravi, Anupam Chattopadhyay, Goutam Paul*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)


As today’s high performance embedded systems are heterogeneous platforms, a crisp boundary between the software and the hardware ciphers is fast getting murky. This work takes up the design of a dedicated hardware accelerator for HC-128, one of the stream ciphers in the software portfolio of eSTREAM finalists. We discuss a novel idea of splitting states kept in SRAMs into multiple smaller SRAMs and exploit the increased parallel accesses to achieve higher throughput.We optimize the accelerator design with state splitting by different factors. A detailed throughput-area-power analysis of these design points follow along with a benchmarking with the state-of-the-art for HC-128. Our implementation marks an HC-128 ASIC with the highest throughput per area performance reported in the literature till date.

Original languageEnglish
Title of host publicationProgress in Cryptology – INDOCRYPT 2014 - 15th International Conference on Cryptology in India, Proceedings
EditorsWilli Meier, Debdeep Mukhopadhyay
Number of pages21
ISBN (Electronic)9783319130385
Publication statusPublished - 01 Jan 2014
Externally publishedYes
Event15th International Conference on Cryptology in India, INDOCRYPT 2014 - New Delhi, India
Duration: 14 Dec 201417 Dec 2014

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Conference15th International Conference on Cryptology in India, INDOCRYPT 2014
CityNew Delhi


  • ASIC
  • Hardware accelerator
  • HC-128
  • Stream cipher implementation

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)


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