Abstract
A novel most significant digit first CORDIC architecture is presented that is suitable for the VLSI design of systolic array processor cells for performing QR decomposition. This is based on an on-line CORDIC algorithm with a constant scale factor and a latency independent of the wordlength. This has been derived through the extension of previously published CORDIC algorithms. It is shown that simplifying the calculation of convergence bounds also greatly simplifies the derivation of suitable VLSI architectures. Design studies, based on a 0.35-µ CMOS standard cell process, indicate that 20 such QR processor cells operating at rates suitable for radar beamfoming can be readily accommodated on a single chip.
Original language | English |
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Pages (from-to) | 592-598 |
Number of pages | 7 |
Journal | IEEE Transactions on Signal Processing |
Volume | 48 |
Issue number | 2 |
DOIs | |
Publication status | Published - 01 Jan 2000 |
Bibliographical note
Copyright 2007 Elsevier B.V., All rights reserved.ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering