Optimisation of source/drain extension region profile for suppression of short channel effects in sub-50 nm DG SOI MOSFETs with high- k gate dielectrics

Abhinav Kranti, Alastair Armstrong

Research output: Contribution to journalArticlepeer-review

29 Citations (Scopus)

Abstract

Novel technology dependent scaling parameters i.e. spacer to gradient ratio and effective channel length (Leff) are proposed for source/drain engineered DG MOSFET, and their significance in minimizing short channel effects (SCES) in high-k gate dielectrics is discussed in detail. Results show that a high-k dielectric should be associated with a higher spacer to gradient ratio to minimise SCEs The analytical model agrees with simulated data over the entire range of spacer widths, doping gradients, high-k gate dielectrics and effective channel lengths.
Original languageEnglish
Article number011
Pages (from-to)1563-1572
Number of pages10
JournalSemiconductor Science and Technology
Volume21(12)
Issue number12
DOIs
Publication statusPublished - 01 Sept 2006

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • General Materials Science
  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics

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